Subject: [PATCH v4 16/32] arm64: KVM: HYP mode world switch implementation

From: [email-masked] (Marc Zyngier)
Date: Tue, 21 May 2013 17:43:20 +0100

On 21/05/13 16:16, Catalin Marinas wrote:
> On Tue, May 14, 2013 at 03:13:44PM +0100, Marc Zyngier wrote:
>> +// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
>> +ENTRY(__kvm_tlb_flush_vmid_ipa)
>> +       kern_hyp_va     x0
>> +       ldr     x2, [x0, #KVM_VTTBR]
>> +       msr     vttbr_el2, x2
>> +       isb
>> +
>> +       /*
>> +        * We could do so much better if we had the VA as well.
>> +        * Instead, we invalidate Stage-2 for this IPA, and the
>> +        * whole of Stage-1. Weep...
>> +        */
>> +       tlbi    ipas2e1is, x1
>> +       dsb     sy
>> +       tlbi    vmalle1is
>> +       dsb     sy
>> +       isb
>> +
>> +       msr     vttbr_el2, xzr
>> +       isb
>> +       ret
>> +ENDPROC(__kvm_tlb_flush_vmid_ipa)
> 
> There are some isbs here which could be removed if you need an eret
> anyway.

There was some discussions a long while ago on kvmarm about keeping
these isbs in we decided to call them from EL2. I could remove them
altogether and only reintroduce them if/when we decide to do that.

>> +ENTRY(__kvm_flush_vm_context)
>> +       tlbi    alle1is
>> +       ic      ialluis
>> +       dsb     sy
>> +       isb
>> +       ret
>> +ENDPROC(__kvm_flush_vm_context)
> 
> I didn't fully understand - why do we need I-cache maintenance here? Is
> it for ASID-tagged VIVT I-cache?

We do that on VMID rollover, as that's basically the only thing we can
do (nuke everything). There's a comment about that in the call site
(arch/arm/arm.c:update_vttbr).

> BTW, the arch/arm equivalent has some better comments on this code ;).

Sure. I'll try to add some more... But this code has much better arm64
support! ;-)

	M.
-- 
Jazz is not dead. It just smells funny...