From: swarren@wwwdotorg•org (Stephen Warren)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 2/3] clk: tegra: T114: add DFLL source clocks
Date: Fri, 07 Jun 2013 10:53:38 -0600 [thread overview]
Message-ID: <51B21012.2030302@wwwdotorg.org> (raw)
In-Reply-To: <20130607121858.21868.73882.stgit@dusk.lan>
On 06/07/2013 06:19 AM, Paul Walmsley wrote:
> Add the input clocks needed by the DFLL IP blocks. Initialize them to
> 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.
>
> This patch is a collaboration with Peter De Schrijver
> <pdeschrijver@nvidia•com>.
>
> Thanks to Laxman Dewangan <ldewangan@nvidia•com> for identifying the
> requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
> issues.
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> @@ -792,6 +794,7 @@ enum tegra114_clk {
> audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
> blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
> xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
> + dfll_ref = 264, dfll_soc,
Those values need to be added to the DT binding documentation, or rather
the header file that now defines the constants for that binding.
BTW, I was rather hoping that Hiroshi would have converted the clock
drivers to actually use that header file by now... Then this requirement
would have been a lot more obvious. Hiroshi, are patches for that coming
soon? Paul, if not, are you able to do that?
For reference, include/dt-bindings/clock/tegra*-car.h.
next prev parent reply other threads:[~2013-06-07 16:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-07 12:18 [PATCH 0/3] clk: tegra: T114: add DFLL prerequisites Paul Walmsley
2013-06-07 12:18 ` [PATCH 1/3] clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL Paul Walmsley
2013-06-07 12:19 ` [PATCH 2/3] clk: tegra: T114: add DFLL source clocks Paul Walmsley
2013-06-07 16:53 ` Stephen Warren [this message]
2013-06-07 12:19 ` [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control Paul Walmsley
2013-06-07 16:57 ` Stephen Warren
2013-06-07 17:06 ` Paul Walmsley
2013-06-11 7:31 ` Prashant Gaikwad
2013-06-11 9:47 ` Paul Walmsley
2013-06-16 4:22 ` Mike Turquette
2013-06-17 20:22 ` Paul Walmsley
2013-06-18 18:28 ` Mike Turquette
2013-06-18 18:33 ` Paul Walmsley
2013-06-19 8:45 ` Peter De Schrijver
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