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From: santosh.shilimkar@ti•com (Santosh Shilimkar)
To: linux-arm-kernel@lists•infradead.org
Subject: [RFC PATCH 1/4] DRIVERS: IRQCHIP: Add crossbar irqchip driver
Date: Thu, 12 Sep 2013 18:51:38 -0400	[thread overview]
Message-ID: <5232457A.8080709@ti.com> (raw)
In-Reply-To: <alpine.DEB.2.02.1309122335440.4089@ionos.tec.linutronix.de>

On Thursday 12 September 2013 06:22 PM, Thomas Gleixner wrote:
> On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
>> Specifically for the IRQ case addressed here, the cross-bar IP
>> sits between the interrupt controller and peripheral interrupts.
>>
>> CPU <-- GIC  <----- CROSSBAR <----- PERIPHERAL IRQs
>>
>> Just to expand it better, cross-bar input IRQ lines are more than
>> what a GIC IRQ controller can support.
>> e.q Total 250 peripheral IRQ lines out of which GIC support
>> only 160 IRQ lines.
>>
>> So the idea here is to dynamically map the IRQ lines at
>> cross-bar level to pick based on request_irq() so that one
>> can optimize the use of limited IRQ lines at the GIC level.
>> Strictly speaking the need is just establish the IRQ
>> connection from peripheral to GIC and thats achieved
>> at the request_irq() level.
>>
>> Earlier approach was to statically build this connections
>> using the DT information in a separate driver probe but
>> it had limitations of fixing the IRQ map and taking away
>> flexibility what this IP provide. 
>>  
>> Hope this gives better picture to you behind the patch
>> series.
> 
> Yes. I halfways understand what you are trying to achieve.
> 
> So CROSSBAR is a routing block between the peripheral and the GIC in
> order to expand the number of possible interrupts.
> 
> Now the real question is, how that expansion mechanism is supposed to
> work. There are two possible scenarios:
> 
> 1) Expand the number of handled interrupts beyond the GIC capacity:
> 
>    That requires a mechanism in CROSSBAR to map several CROSSBAR
>    interrupts to a particular GIC interrupt and provide a demux
>    mechanism to invoke the shared handlers.
> 
This is not possible in hardware and not supported. Hardware has
no notion of muxing multiple IRQ's to generate 1 IRQ or ack etc
functionality. Its a simple MUX to tie knots between input and output
wires.

> 2) Provide a mapping mechanism between possibly 250 interrupt numbers
>    and a limitation of a total 160 active interrupts by the underlying
>    GIC.
> 
This is the need and problem we are trying to solve.

Regards,
Santosh

  reply	other threads:[~2013-09-12 22:51 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-09-12 15:39 [RFC PATCH 0/4] DRIVERS: IRQCHIP: Add crossbar irqchip driver Sricharan R
2013-09-12 15:39 ` [RFC PATCH 1/4] " Sricharan R
2013-09-12 20:18   ` Thomas Gleixner
2013-09-12 20:48     ` Santosh Shilimkar
2013-09-12 22:22       ` Thomas Gleixner
2013-09-12 22:51         ` Santosh Shilimkar [this message]
2013-09-13  0:26           ` Thomas Gleixner
2013-09-13  1:42             ` Santosh Shilimkar
2013-09-13  8:32               ` Sricharan R
2013-09-13 14:24               ` Thomas Gleixner
2013-09-13 14:55                 ` Santosh Shilimkar
2013-09-18 15:07                   ` Santosh Shilimkar
2013-09-18 22:31                     ` Thomas Gleixner
2013-09-17 12:26                 ` Linus Walleij
2013-09-18 13:52                   ` Sricharan R
2013-09-18 15:25                     ` Sricharan R
2013-09-18 22:13                       ` Thomas Gleixner
2013-09-12 20:54   ` Felipe Balbi
2013-09-12 21:35     ` Thomas Gleixner
2013-09-12 22:12       ` Thomas Gleixner
2013-09-20  8:58   ` Mark Rutland
2013-09-20  9:59     ` Sricharan R
2013-09-12 15:39 ` [RFC PATCH 2/4] ARM: DTS: DRA: Add crossbar device binding Sricharan R
2013-09-12 15:39 ` [RFC PATCH 3/4] ARM: DTS: DRA: Replace peripheral interrupt numbers with crossbar inputs Sricharan R
2013-09-12 15:39 ` [RFC PATCH 4/4] ARM: DRA: Kconfig: Enable crossbar irqchip driver for DRA7xx Sricharan R

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