Subject: [PATCHv4 4/7] iommu/tegra: smmu: Calculate ASID register offset by ID

From: [email-masked] (Stephen Warren)
Date: Tue, 12 Nov 2013 17:02:28 -0700

On 11/11/2013 01:31 AM, Hiroshi Doyu wrote:
> ASID register offset is caclulated by SWGROUP ID so that we can get
> rid of old SoC specific MACROs. This ID conversion is needed for the
> unified SMMU driver over Tegra SoCs. We use dt-bindings MACRO instead
> of SoC dependent MACROs. The formula is:
> 
>   MC_SMMU_<swgroup name>_ASID_0 = MC_SMMU_AFI_ASID_0 + ID * 4;
> 
> Now SWGROUP ID is the global HardWare Accelerator(HWA) identifier
> among all Tegra SoC except Tegra2.

> diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c

I would suggest deleting the following too, since they are presumably
specific to a single SoC:

> #define SMMU_AFI_ASID   0x238   /* PCIE */
> #define SMMU_AVPC_ASID  0x23c   /* AVP */
> #define SMMU_DC_ASID    0x240   /* Display controller */
> #define SMMU_DCB_ASID   0x244   /* Display controller B */
> #define SMMU_EPP_ASID   0x248   /* Encoder pre-processor */
> #define SMMU_G2_ASID    0x24c   /* 2D engine */
> #define SMMU_HC_ASID    0x250   /* Host1x */
> #define SMMU_HDA_ASID   0x254   /* High-def audio */
> #define SMMU_ISP_ASID   0x258   /* Image signal processor */
> #define SMMU_MPE_ASID   0x264   /* MPEG encoder */
> #define SMMU_NV_ASID    0x268   /* (3D) */
> #define SMMU_NV2_ASID   0x26c   /* (3D) */
> #define SMMU_PPCS_ASID  0x270   /* AHB */
> #define SMMU_SATA_ASID  0x278   /* SATA */
> #define SMMU_VDE_ASID   0x27c   /* Video decoder */
> #define SMMU_VI_ASID    0x280   /* Video input */

> +#define HWGRP_ASID_REG(x) ((x) * sizeof(u32) + SMMU_AFI_ASID)

Also, I would suggest renaming SMMU_AFI_ASID to something more like
SMMU_ASID_0 or SMMU_ASID_BASE so as not to call it the AFI register,
since presumably the whole point of this patch is that there's no
guarantee that register is the AFI ASId in all SoCs?