Subject: [PATCH 2/2] memory: ti-aemif: add bindings for AEMIF driver

From: [email-masked] (ivan.khoronzhuk)
Date: Tue, 26 Nov 2013 19:23:00 +0200

On 11/22/2013 11:06 PM, Kumar Gala wrote:
>
> On Nov 20, 2013, at 1:03 PM, ivan.khoronzhuk <[email-masked]> wrote:
>
>> On 11/20/2013 08:21 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> +				the chip select signal.
>>>> +				Minimum value is 1 (0 treated as 1).
>>>> +
>>>> +- ti,cs-wsetup:		write setup width, ns
>>>> +				Time between the beginning of a memory cycle
>>>> +				and the activation of write strobe.
>>>> +				Minimum value is 1 (0 treated as 1).
>>>> +
>>>> +- ti,cs-wstrobe:	write strobe width, ns
>>>> +				Time between the activation and deactivation of
>>>> +				the write strobe.
>>>> +				Minimum value is 1 (0 treated as 1).
>>>> +
>>>> +- ti,cs-whold:		write hold width, ns
>>>> +				Time between the deactivation of the write
>>>> +				strobe and the end of the cycle (which may be
>>>> +				either an address change or the deactivation of
>>>> +				the chip select signal.
>>>> +				Minimum value is 1 (0 treated as 1).
>>>> +
>>>> +If any of the above parameters are absent, current parameter value will be taken
>>>> +from the corresponding HW reg.
>>>> +
>>>> +The name for cs node must be in format csN, where N is the cs number.
>>>
>>> this is wired we should use reg instead to represent the cs as done for SPI
>>> or a an other property
>>>
>>> Best Regards,
>>> J.
>>>
>>
>> Ok, I will add new property cs-chipselect like following :
>>
>> ti,cs-chipselect:	number of chipselect. Indicates on the
>> 			aemif driver which chipselect is used
>> 			for accessing the memory.
>> 			For compatibles "ti,davinci-aemif" and
>> 			"ti,keystone-aemif" it can be in range [0-3].
>> 			For compatible "ti,omap-L138-aemif" range is [2-5].
>>
>> Is it OK?
>
> Why do you need this? As it was mentioned just use reg:
>
> So you?d have something like:
>
> memory-controller at 21000A00 {
> 	?
> 	nand:cs2 at 2 {
> 		reg = <2 0 0>;
> 		ranges;
> 		...
>
> 	}:
> };
>
> However, I?m confused by the example in which you have:
>
> +		nand at 0,0x8000000 {
> +			compatible = "ti,davinci-nand";
> +			reg = <0 0x8000000 0x4000000
It means, use memory of 0 AEMIF range beginning from 0x800000 (started 
from beginning of this range) and with size 0x4000000
> +			       1 0x0000000 0x0000100>;
It means, use memory of 1 AEMIF range + 0x0000000 and with size 0x0000100
> +
> +			.. see davinci-nand.txt
> +		};
>
> What chipselects is this on 0 & 1?
Any of them is not cs number. 0 - is just a memory range number.
> - k

The ranges property provides a means of defining a mapping or 
translation between the address space of the AEMIF and the address space 
of the cs nodes.

The reg property describes the address of the cs's resources within the 
address space defined by AEMIF. The reg is the memory range, not cs number.

See Grygorii Starshko comment on it, he described it very well.
			
>>
>> --
>> Regards,
>> Ivan Khoronzhuk
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>

-- 
Regards,
Ivan Khoronzhuk