Subject: questions of cpuidle

From: [email-masked] (Daniel Lezcano)
Date: Tue, 10 Dec 2013 09:25:16 +0100

On 12/10/2013 09:07 AM, anish singh wrote:
> On Mon, Dec 9, 2013 at 11:27 PM, Daniel Lezcano
> <[email-masked]> wrote:
>> On 12/10/2013 07:33 AM, Alex Shi wrote:
>>>
>>> On 12/09/2013 10:17 PM, Daniel Lezcano wrote:
>>>>
>>>>
>>>> Concerning the wake up of the cpu: the cpu disabled the irq and
>>>> goes to sleep, it is up to the firmware to wake up the cpu when an
>>>> interrupt occurs. It will exits its sleep state, call
>>>> clock_events_notify(EXIT), by this way re-switching to the local
>>>> timer, and then re-enabling the local interrupt which leads to the
>>>> interrupt handler.
>>>
>>>
>>> Thanks a lots for excellent article and detailed explains!
>>>
>>> So, if the firmware is in response to wake up cpu. that means there
>>> is a unit which control the firmware and it can not be power down.
>>
>>
>> Correct.
>>
>>
>>> Do you know which unit running the firmware to wake up deep idle
>>> CPU.
>>
>>
>> That depends on the SoC implementation.
> and which is intentionally kept hidden away.
>>
>> Some SoC have a "Power Management Unit". The PMU has several idle states
>> defined, each of them are described in the technical reference manual
>> (TRM) with the wake up sources.
> PMU is intentionally kept hidden by OEM companies as this way
> they protect there hardware IP.

Unfortunately yes and beside that hiding the bugs in a black box letting 
the user/developer to bang its head against the walls :)

>> Some SoC don't have any PMU and the idle states are very few, keeping
>> most of the logic on.
>>
>> Some other SoC hide the PMU behind PSCI calls.
> which is intentional.
>>> And does the wake up pass via GIC to CPU? If so, does the GIC need
>>> keep awake when all cpu idle? If not, how the firmware give the
>>> interrupt to CPU? And I am wondering if the deep idle cpu voltage get
>>> to near 0. How the cpu get the interrupt signal?
>>
>>
>> If a deep idle state powers down the GIC, it is up to the PMU to proxy
>> the interrupts. When an interrupt occurs, the PMU powers up the logic,
>> including the GIC. The notifier call chain with cpu_suspend / cpu_resume
>> will save and restore the GIC registers.
>>
>> But this is hardware specific and will depend on how the PMU is
>> implemented and how far it goes in the power management.
>>
>> You have a good example in the drivers/cpuidle/cpuidle-ux500.c to
>> understand with the comments how the interrupts are handled through the
>> power management unit.
>>
>> In the Xillinx documentation available on the web [1], the chapter 24.4
>> gives the information about one kind of PMU.
>>
>> I believe the mechanism is pretty similar on all the hardware but it is
>> obfuscated by a generic power instruction like mwait.
>>
>>    -- Daniel
>>
>> [1]
>> http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
>>
>>
>>
>>>> There are some more informations in the wiki page [1].
>>>>
>>>> -- Daniel
>>>>
>>>> [1]
>>>> https://wiki.linaro.org/WorkingGroups/PowerManagement/Doc/WakeUpSources
>>>
>>>
>>>>
>>>
>>
>>
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