Subject: [PATCH v2 01/11] clk: sunxi: register factors clocks behind composite

From: [email-masked] (Emilio López)
Date: Wed, 18 Dec 2013 08:27:48 -0300

Hi Mike,

Thanks for the prompt review! It's much appreciated.

El 17/12/13 23:55, Mike Turquette escribi?:
> Quoting Emilio L?pez (2013-12-17 16:44:53)
>> This commit reworks factors clock registration to be done behind a
>> composite clock. This allows us to additionally add a gate, mux or
>> divisors, as it will be needed by some future PLLs.
>>
>> Signed-off-by: Emilio L?pez <[email-masked]>
>> Acked-by: Maxime Ripard <[email-masked]>
>> ---
(...)
> Seems like 5 is a magic number? I guess this type of clock always has
> the same number of parents? Might be good to use a preprocessor macro
> here.

Indeed, these clocks always have less than 5 parents. I'll use a macro 
to make it clearer.

Cheers,

Emilio