Subject: [PATCH 1/4] clk: sunxi: Allwinner A20 output clock support

From: [email-masked] (Emilio López)
Date: Mon, 23 Dec 2013 13:23:47 -0300

Hi again,

El 23/12/13 13:13, Emilio L?pez escribi?:
> Hi,
>
> El 23/12/13 05:37, Chen-Yu Tsai escribi?:
>> This patch adds support for the external clock outputs on the
>> Allwinner A20 SoC. The clock outputs are similar to "module 0"
>> type clocks, with different offsets and widths for clock factors.
>>
>> Signed-off-by: Chen-Yu Tsai <[email-masked]>
>
> This patch looks good to me,
>
> Acked-by: Emilio L?pez <[email-masked]>
>
>> ---
>>   drivers/clk/sunxi/clk-sunxi.c | 57
>> +++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 57 insertions(+)

Please add the new binding to the binding document; I just noticed it 
was missing. You can keep the Ack once you do so.

Cheers,

Emilio