Subject: [PATCH v3 2/5] irqchip: gic: use dmb ishst instead of dsb when raising a softirq

From: [email-masked] (Marc Zyngier)
Date: Wed, 19 Feb 2014 13:21:04 +0000

On 19/02/14 12:28, Will Deacon wrote:
> When sending an SGI to another CPU, we require a barrier to ensure that
> any pending stores to normal memory are made visible to the recipient
> before the interrupt arrives.
> 
> Rather than use a vanilla dsb() (which will soon cause an assembly error
> on arm64) before the writel_relaxed, we can instead use dsb(ishst),
> since we just need to ensure that any pending normal writes are visible
> within the inner-shareable domain before we poke the GIC.
> 
> With this observation, we can then further weaken the barrier to a
> dmb(ishst), since other CPUs in the inner-shareable domain must observe
> the write to the distributor before the SGI is generated.
> 
> Cc: Thomas Gleixner <[email-masked]>
> Cc: Marc Zyngier <[email-masked]>
> Cc: Catalin Marinas <[email-masked]>
> Signed-off-by: Will Deacon <[email-masked]>

Acked-by: Marc Zyngier <[email-masked]>

I'll queue a similar fix for the GICv3 code.

Thanks,

	M.
-- 
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