From: george.cherian@ti•com (George Cherian)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync
Date: Mon, 28 Apr 2014 18:28:07 +0530 [thread overview]
Message-ID: <535E505F.3010302@ti.com> (raw)
In-Reply-To: <20140428075530.GA8371@netboy>
On 4/28/2014 1:25 PM, Richard Cochran wrote:
> On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote:
>> Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
>> With this enabled the L2 PTP is working.
> L2 works fine without this bit. If this is needed for V3 hardware,
> then it should have its own code variant.
okay
>
>> while at that rename TS_BIT8 to TS_TTL_NONZERO
> Is this bit finally documented for am335x?
Not for am335x, but for other SoC's it s documented.
> Thanks,
> Richard
>
--
-George
next prev parent reply other threads:[~2014-04-28 12:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-28 4:10 [PATCH 0/6] Add CPTS support for AM437x George Cherian
2014-04-28 4:10 ` [PATCH 1/6] drivers: net: cpts: Remove hardcoded clock name for CPTS George Cherian
2014-04-28 6:55 ` Richard Cochran
2014-04-28 14:31 ` Felipe Balbi
2014-04-28 14:45 ` George Cherian
2014-04-28 4:10 ` [PATCH 2/6] ARM: dts: am33xx: Add clock names for cpsw and cpts George Cherian
2014-04-28 4:10 ` [PATCH 3/6] drivers: net: cpsw: Enable CPTS for DRA7xx and AM4372 George Cherian
2014-04-28 4:10 ` [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync George Cherian
2014-04-28 7:55 ` Richard Cochran
2014-04-28 12:58 ` George Cherian [this message]
2014-04-28 4:10 ` [PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk George Cherian
2014-04-28 7:10 ` Richard Cochran
2014-04-28 12:55 ` George Cherian
2014-04-28 16:18 ` Richard Cochran
2014-04-29 4:28 ` George Cherian
2014-04-28 4:10 ` [PATCH 6/6] ARM: dts: am4372: Add clock names for cpsw and cpts George Cherian
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