From: t.figa@samsung•com (Tomasz Figa)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH RFC 3/4] clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
Date: Fri, 16 May 2014 12:52:45 +0200 [thread overview]
Message-ID: <5375EDFD.1020708@samsung.com> (raw)
In-Reply-To: <CAPdUM4P7Z1eLVKuc0N1iPaekM_7kNv7KCve2MgrEziszfnzz7A@mail.gmail.com>
Hi Rahul,
On 16.05.2014 12:39, Rahul Sharma wrote:
> [snip]
>> + gate->lock = &clkout_lock;
>> +
>> + mux->reg = reg + EXYNOS_PMU_DEBUG_REG;
>> + mux->mask = EXYNOS_CLKOUT_MUX_MASK;
>> + mux->shift = EXYNOS_CLKOUT_MUX_SHIFT;
>> + mux->lock = &clkout_lock;
>> +
>> + clk = clk_register_composite(NULL, "clkout", parent_names,
>> + parent_count, &mux->hw,
>> + &clk_mux_ops, NULL, NULL, &gate->hw,
>> + &clk_gate_ops, 0);
>> + if (IS_ERR(clk))
>> + goto err_unmap;
>> +
>
> Hi Tomasz,
>
> Do we really need a composite clock here? How about registering
> a mux and a gate separately?
What's wrong with a composite clock? It simplifies the code as just a
single clock needs to be registered. I don't see any drawbacks compared
to registering two clocks separately.
Best regards,
Tomasz
next prev parent reply other threads:[~2014-05-16 10:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-15 17:32 [PATCH RFC 0/4] Add support for Exynos clock output configuration Tomasz Figa
2014-05-15 17:32 ` [PATCH RFC 1/4] clk: samsung: exynos4: Add missing DMC clock hierarchy Tomasz Figa
2014-05-15 17:32 ` [PATCH RFC 2/4] clk: samsung: exynos4: Add CLKOUT " Tomasz Figa
2014-05-15 17:32 ` [PATCH RFC 3/4] clk: samsung: Add driver to control CLKOUT line on Exynos SoCs Tomasz Figa
2014-05-16 10:39 ` Rahul Sharma
2014-05-16 10:52 ` Tomasz Figa [this message]
2014-05-16 14:35 ` Rahul Sharma
2014-05-16 14:58 ` Tomasz Figa
2014-05-16 23:04 ` Mike Turquette
2014-05-19 7:16 ` Tushar Behera
2014-05-19 10:25 ` Tomasz Figa
2014-05-15 17:32 ` [PATCH RFC 4/4] ARM: dts: exynos: Update PMU node with CLKOUT related data Tomasz Figa
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