From: kishon@ti•com (Kishon Vijay Abraham I)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v2 04/18] PCI: designware: use untranslated address while programming ATU
Date: Wed, 18 Jun 2014 14:38:43 +0530 [thread overview]
Message-ID: <53A1571B.7080806@ti.com> (raw)
In-Reply-To: <1401345500-20188-5-git-send-email-kishon@ti.com>
Hi Arnd,
On Thursday 29 May 2014 12:08 PM, Kishon Vijay Abraham I wrote:
> In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
> address. So whenever the cpu issues a read/write request, the 4 most
> significant bits are used by L3 to determine the target controller.
> For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe controller but
> the PCIe controller will see only (0x000_0000 - 0xFFF_FFF). So for programming
> the outbound translation window the *base* should be programmed as 0x000_0000.
> Whenever we try to write to say 0x2000_0000, it will be translated to whatever
> we have programmed in the translation window with base as 0x000_0000.
>
> This is needed when the dt node is modelled something like below
> axi {
> compatible = "simple-bus";
> #size-cells = <1>;
> #address-cells = <1>;
> ranges = <0x0 0x20000000 0x10000000 // 28-bit bus
> 0x51000000 0x51000000 0x3000>;
> pcie at 51000000 {
> reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
> reg-names = "config", "ti_conf", "rc_dbics";
> #address-cells = <3>;
> #size-cells = <2>;
> ranges = <0x81000000 0 0 0x03000 0 0x00010000
> 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
> };
> };
>
> Here the CPU address for configuration space is 0x20013000 and the controller
> address for configuration space is 0x13000. The controller address should be
> used while programming the ATU (in order for translation to happen properly in
> DRA7xx).
I've fixed this up with what you suggested in the v1 of the series. Do you
think this is fine?
Thanks
Kishon
>
> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch•com>
> Cc: Bjorn Helgaas <bhelgaas@google•com>
> Cc: Mohit Kumar <mohit.kumar@st•com>
> Cc: Jingoo Han <jg1.han@samsung•com>
> Cc: Marek Vasut <marex@denx•de>
> Cc: Arnd Bergmann <arnd@arndb•de>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti•com>
> ---
> drivers/pci/host/pcie-designware.c | 49 ++++++++++++++++++++++++++++--------
> drivers/pci/host/pcie-designware.h | 4 +++
> 2 files changed, 42 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 603b386..9dfd2d4 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -397,8 +397,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> struct of_pci_range range;
> struct of_pci_range_parser parser;
> struct resource *cfg_res;
> - u32 val;
> - int i;
> + u32 val, na, ns;
> + const __be32 *addrp;
> + int i, index;
> +
> + /* Find the address cell size and the number of cells in order to get
> + * the untranslated address.
> + */
> + of_property_read_u32(np, "#address-cells", &na);
> + ns = of_n_size_cells(np);
>
> cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> if (cfg_res) {
> @@ -406,6 +413,12 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> pp->config.cfg1_size = resource_size(cfg_res)/2;
> pp->cfg0_base = cfg_res->start;
> pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
> +
> + /* Find the untranslated configuration space address */
> + index = of_property_match_string(np, "reg-names", "config");
> + addrp = of_get_address(np, index, false, false);
> + pp->cfg0_mod_addr = of_read_number(addrp, ns);
> + pp->cfg1_mod_addr = pp->cfg0_mod_addr + pp->config.cfg0_size;
> } else {
> dev_err(pp->dev, "missing *config* reg space\n");
> }
> @@ -431,12 +444,20 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> pp->config.io_size = resource_size(&pp->io);
> pp->config.io_bus_addr = range.pci_addr;
> pp->io_base = range.cpu_addr;
> +
> + /* Find the untranslated IO space address */
> + pp->io_mod_addr = of_read_number(parser.range -
> + parser.np + na, ns);
> }
> if (restype == IORESOURCE_MEM) {
> of_pci_range_to_resource(&range, np, &pp->mem);
> pp->mem.name = "MEM";
> pp->config.mem_size = resource_size(&pp->mem);
> pp->config.mem_bus_addr = range.pci_addr;
> +
> + /* Find the untranslated MEM space address */
> + pp->mem_mod_addr = of_read_number(parser.range -
> + parser.np + na, ns);
> }
> if (restype == 0) {
> of_pci_range_to_resource(&range, np, &pp->cfg);
> @@ -444,6 +465,12 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> pp->config.cfg1_size = resource_size(&pp->cfg)/2;
> pp->cfg0_base = pp->cfg.start;
> pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> +
> + /* Find the untranslated configuration space address */
> + pp->cfg0_mod_addr = of_read_number(parser.range -
> + parser.np + na, ns);
> + pp->cfg1_mod_addr = pp->cfg0_mod_addr +
> + pp->config.cfg0_size;
> }
> }
>
> @@ -518,9 +545,9 @@ static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
> /* Program viewport 0 : OUTBOUND : CFG0 */
> dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
> PCIE_ATU_VIEWPORT);
> - dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
> - dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
> - dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
> + dw_pcie_writel_rc(pp, pp->cfg0_mod_addr, PCIE_ATU_LOWER_BASE);
> + dw_pcie_writel_rc(pp, (pp->cfg0_mod_addr >> 32), PCIE_ATU_UPPER_BASE);
> + dw_pcie_writel_rc(pp, pp->cfg0_mod_addr + pp->config.cfg0_size - 1,
> PCIE_ATU_LIMIT);
> dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
> dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
> @@ -534,9 +561,9 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
> dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
> PCIE_ATU_VIEWPORT);
> dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
> - dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
> - dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
> - dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
> + dw_pcie_writel_rc(pp, pp->cfg1_mod_addr, PCIE_ATU_LOWER_BASE);
> + dw_pcie_writel_rc(pp, (pp->cfg1_mod_addr >> 32), PCIE_ATU_UPPER_BASE);
> + dw_pcie_writel_rc(pp, pp->cfg1_mod_addr + pp->config.cfg1_size - 1,
> PCIE_ATU_LIMIT);
> dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
> dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
> @@ -549,9 +576,9 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
> dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
> PCIE_ATU_VIEWPORT);
> dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
> - dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
> - dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
> - dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
> + dw_pcie_writel_rc(pp, pp->mem_mod_addr, PCIE_ATU_LOWER_BASE);
> + dw_pcie_writel_rc(pp, (pp->mem_mod_addr >> 32), PCIE_ATU_UPPER_BASE);
> + dw_pcie_writel_rc(pp, pp->mem_mod_addr + pp->config.mem_size - 1,
> PCIE_ATU_LIMIT);
> dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
> dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index 3063b35..d1f7d5e 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -36,11 +36,15 @@ struct pcie_port {
> u8 root_bus_nr;
> void __iomem *dbi_base;
> u64 cfg0_base;
> + u64 cfg0_mod_addr;
> void __iomem *va_cfg0_base;
> u64 cfg1_base;
> + u64 cfg1_mod_addr;
> void __iomem *va_cfg1_base;
> u64 io_base;
> + u64 io_mod_addr;
> u64 mem_base;
> + u64 mem_mod_addr;
> spinlock_t conf_lock;
> struct resource cfg;
> struct resource io;
>
next prev parent reply other threads:[~2014-06-18 9:08 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-29 6:38 [PATCH v2 00/18] PCIe support for DRA7xx Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 01/18] phy: phy-omap-pipe3: Add support for PCIe PHY Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 02/18] phy: pipe3: insert delay to enumerate in GEN2 mode Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg' Kishon Vijay Abraham I
2014-05-29 7:11 ` Mohit KUMAR DCG
2014-05-29 13:16 ` Kishon Vijay Abraham I
2014-05-29 15:03 ` Kumar Gala
2014-05-29 15:18 ` Liviu Dudau
2014-05-29 16:03 ` Kumar Gala
2014-05-29 16:30 ` Jason Gunthorpe
2014-05-29 16:51 ` Kumar Gala
2014-05-29 16:32 ` Murali Karicheri
2014-05-30 5:30 ` Kishon Vijay Abraham I
2014-05-30 14:15 ` Karicheri, Muralidharan
2014-06-18 9:14 ` Kishon Vijay Abraham I
2014-06-18 9:27 ` Jingoo Han
2014-05-29 6:38 ` [PATCH v2 04/18] PCI: designware: use untranslated address while programming ATU Kishon Vijay Abraham I
2014-06-18 9:08 ` Kishon Vijay Abraham I [this message]
2014-06-20 16:18 ` Arnd Bergmann
2014-06-20 17:45 ` Rob Herring
2014-06-20 18:54 ` Arnd Bergmann
2014-05-29 6:38 ` [PATCH v2 05/18] PCI: host: pcie-dra7xx: add support for pcie-dra7xx controller Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 06/18] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-06-19 11:10 ` Tero Kristo
2014-06-19 12:45 ` Kishon Vijay Abraham I
2014-06-19 13:27 ` Tero Kristo
2014-05-29 6:38 ` [PATCH v2 07/18] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
2014-06-19 11:12 ` Tero Kristo
2014-06-19 13:00 ` Kishon Vijay Abraham I
2014-06-19 13:24 ` Tero Kristo
2014-05-29 6:38 ` [PATCH v2 08/18] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 09/18] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY Kishon Vijay Abraham I
2014-06-19 11:16 ` Tero Kristo
2014-06-19 13:23 ` Kishon Vijay Abraham I
2014-06-19 13:26 ` Tero Kristo
2014-05-29 6:38 ` [PATCH v2 11/18] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 12/18] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe " Kishon Vijay Abraham I
2014-06-19 11:20 ` Tero Kristo
2014-06-19 13:25 ` Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 14/18] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 15/18] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
2014-05-29 6:38 ` [PATCH v2 16/18] ARM: OMAP: Enable PCI for DRA7 Kishon Vijay Abraham I
2014-05-29 6:48 ` Jingoo Han
2014-05-29 13:17 ` Kishon Vijay Abraham I
2014-05-29 17:52 ` Rob Herring
2014-05-29 17:54 ` Will Deacon
2014-05-29 6:38 ` [TEMP PATCH v2 17/18] PCI: host: pcie-dra7xx: use reset framework APIs to reset PCIe Kishon Vijay Abraham I
2014-05-29 6:38 ` [TEMP PATCH v2 18/18] ARM: dts: dra7: Add *resets* property for PCIe dt node Kishon Vijay Abraham I
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