Subject: [PATCH] clk: sunxi: add correct divider table for sun4i-apb0 clock

From: [email-masked] (Emilio López)
Date: Sat, 06 Sep 2014 12:55:18 -0300

Hi,

El 06/09/14 a las 03:45, Chen-Yu Tsai escibi?:
> The sun4i-apb0 clock, as found on all platforms using it, is a
> power-of-two-based divider clock, with a special divider of 2
> for value 0.
>
> This was causing the clock framework to incorrectly calculate
> the clock rate for apb1 and related modules on sun6i and sun8i.
> On sun[4/5/7]i, u-boot SPL configures the divider with value 1
> for /2 divider, so no suprises there.
>
> This patch adds a proper divider table for it, so the correct
> clock rate can be calculated.
>
> Signed-off-by: Chen-Yu Tsai <[email-masked]>

 From a quick look at the A10 manual,

Acked-by: Emilio L?pez <[email-masked]>

I'll see about testing it on hardware today/tomorrow

Thanks!

Emilio