From: kever.yang@rock-chips•com (Kever Yang)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH] clk: rockchip: add missing rk3288 npll rate table
Date: Thu, 25 Sep 2014 09:36:47 +0800 [thread overview]
Message-ID: <542371AF.6030103@rock-chips.com> (raw)
In-Reply-To: <1631893.xHvKLXVMyM@phil>
Heiko,
On 09/25/2014 05:41 AM, Heiko St?bner wrote:
> The npll on rk3288 is exactly the same pll type as the other 4. Yet it
> was missing the link to the rate table, making rate changes impossible.
> Change that by setting the table.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech•de>
> ---
> drivers/clk/rockchip/clk-rk3288.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> index 8ea885b..938d30b 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -143,7 +143,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
> [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
> RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
> [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
> - RK3288_MODE_CON, 14, 9, NULL),
> + RK3288_MODE_CON, 14, 9, rk3288_pll_rates),
> };
>
> static struct clk_div_table div_hclk_cpu_t[] = {
Tested-by: Kever Yang <kever.yang@rock-chips•com>
next prev parent reply other threads:[~2014-09-25 1:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-24 21:41 [PATCH] clk: rockchip: add missing rk3288 npll rate table Heiko Stübner
2014-09-24 22:51 ` Doug Anderson
2014-09-25 1:35 ` Kever Yang
2014-09-25 3:56 ` Doug Anderson
2014-09-25 1:36 ` Kever Yang [this message]
2014-09-25 21:49 ` Mike Turquette
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