Subject: [PATCH 5/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC

From: [email-masked] (Ezequiel Garcia)
Date: Thu, 23 Oct 2014 08:51:27 -0300

On 10/23/2014 06:14 AM, Thomas Petazzoni wrote:
> Dear Ezequiel Garcia,
> 
> On Wed, 22 Oct 2014 19:16:42 -0300, Ezequiel Garcia wrote:
> 
>> The <mpic 3> is a per CPU interrupt.
>>
>> Actually, the interrupt contains more than just PMU events, it contains
>> a summary of several CPU events: Perf counters for each CPU, Power
>> management interrupts for each CPU, L2 cache interrupt, among others.
> 
> This is kind of a side discussion but if this <mpic 3> interrupts does
> much more than PMU events, then we should implement a separate irqchip
> driver for this, to "demultiplex" the events notified by this interrupt.
> 

Oh, I didn't realize this was possible.

> Yes, today we are only using the PMU events from <mpic 3>, but what if
> tomorrow we need to be notified of other events in other drivers? We
> would be screwed, because we would have to change the DT
> representation: the PMU would no longer take <&mpic 3> as the
> interrupt, but <&some_other_irq_controller XYZ> as the interrupt.
> 

Yes, that sounds like a much better approach. I'll take a look and try
to prepare something.

-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com