Subject: [PATCH 5/7] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC

From: [email-masked] (Ezequiel Garcia)
Date: Thu, 23 Oct 2014 09:19:15 -0300

On 10/23/2014 09:07 AM, Thomas Petazzoni wrote:
> Dear Ezequiel Garcia,
> 
> On Thu, 23 Oct 2014 08:51:27 -0300, Ezequiel Garcia wrote:
> 
>>> On Wed, 22 Oct 2014 19:16:42 -0300, Ezequiel Garcia wrote:
>>>
>>>> The <mpic 3> is a per CPU interrupt.
>>>>
>>>> Actually, the interrupt contains more than just PMU events, it contains
>>>> a summary of several CPU events: Perf counters for each CPU, Power
>>>> management interrupts for each CPU, L2 cache interrupt, among others.
>>>
>>> This is kind of a side discussion but if this <mpic 3> interrupts does
>>> much more than PMU events, then we should implement a separate irqchip
>>> driver for this, to "demultiplex" the events notified by this interrupt.
>>
>> Oh, I didn't realize this was possible.
> 
> The only trick is that it can't be a separate DT node, because the
> registers that contains the mask/cause informations for the events
> notified by <mpic 3> belongs to the MPIC registers area.
> 

Technically speaking, we can stop requesting the region in the mpic
irqchip driver and share the registers, just as we do in other drivers.

Not the most elegant thing to do, though.
-- 
Ezequiel Garc?a, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com