Subject: [PATCH v4 05/12] memory: Add NVIDIA Tegra memory controller support

From: [email-masked] (Terje Bergström)
Date: Thu, 30 Oct 2014 12:18:37 +0200

On 30.10.2014 12:03, Alexandre Courbot wrote:
> I had to change the .reg of TEGRA_SWGROUP_GPU to 0xaac to get the IOMMU
> to work with GK20A. The reason is still not completely clear to me, but
> if you look at the TRM you see that 0xaa8 is basically constant, with
> the SMMU translation bit hardcoded to DISABLE (and the ASID field being
> meaningless in that case). However right after that register you have a
> functional one named GPUB instead of GPU, and this one is fully
> writeable (and has the expected effect).

GPU has two SW group IDs, because it accesses memory both with and
without translation. The bit 34 in addresses in f.ex. PTE chooses
between the two.

GPU is hard-wired to disable translation. For GPUB translation can be
enabled.

Terje