From: arnd@arndb•de (Arnd Bergmann)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w
Date: Fri, 18 Jul 2014 21:50:08 +0200 [thread overview]
Message-ID: <5467203.eMVRoNeSx1@wuerfel> (raw)
In-Reply-To: <CAL_JsqKheoWrSGtxPO=AE8g9iOAqfwRa=81Ku=Cfx8_gpDysOg@mail.gmail.com>
On Friday 18 July 2014 14:31:39 Rob Herring wrote:
> > +
> > + Example:
> > + pcie_msi_intc: msi-interrupt-controller {
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
> > + };
> > +
> > +pcie_intc: Interrupt controller device node for Legacy irq chip
> > + interrupt-cells: should be set to 1
> > + interrupt-parent: Parent interrupt controller phandle
> > + interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
> > +
> > + Example:
> > + pcie_intc: legacy-interrupt-controller {
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
> > + };
>
> This seems wrong. Legacy interrupts should be described with
> interrupt-map and then PCI child devices have a standard interrupt
> specifier.
>
> I'm not sure about MSIs, but I would think they would have a standard
> format too.
>
IIRC, it's actually the correct way to do this here: the problem is that
the PCI IRQs are not directly connected to the GIC, but instead there is
a nested irqchip that has each PCI IRQ routed to it and that requires
an extra EOI for each interrupt.
The interrupt-map in the PCI host points to this special irqchip rather
than to the GIC.
Arnd
next prev parent reply other threads:[~2014-07-18 19:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-18 15:14 [PATCH v6 0/5] Add Keystone PCIe controller driver Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 1/5] PCI: designware: add rd[wr]_other_conf API Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 2/5] PCI: designware: refactor MSI code to work with v3.65 dw hardware Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 3/5] PCI: designware: enhance dw_pcie_host_init() to support v3.65 DW hardware Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w Murali Karicheri
2014-07-18 19:31 ` Rob Herring
2014-07-18 19:50 ` Arnd Bergmann [this message]
2014-07-18 20:15 ` Murali Karicheri
2014-07-22 15:37 ` Rob Herring
2014-07-22 19:00 ` Murali Karicheri
2014-07-18 20:29 ` Murali Karicheri
2014-07-21 1:44 ` Jingoo Han
2014-07-21 16:39 ` Murali Karicheri
2014-07-22 15:41 ` Rob Herring
2014-07-22 18:58 ` Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 5/5] PCI: keystone: Update maintainer information Murali Karicheri
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