Subject: [PATCH v4 1/3] clk: samsung: Fix clock disable failure because domain being gated

From: [email-masked] (Sylwester Nawrocki)
Date: Fri, 05 Dec 2014 12:22:02 +0100

Javier,

On 05/12/14 12:00, Krzysztof Kozlowski wrote:
> Audio subsystem clocks are located in separate block. If clock for this
> block (from main clock domain) 'mau_epll' is gated then any read or
> write to audss registers will block.
> 
> This was observed on Exynos 5420 platforms (Arndale Octa and Peach
> Pi/Pit) after introducing runtime PM to pl330 DMA driver. After that
> commit the 'mau_epll' was gated, because the "amba" clock was disabled
> and there were no more users of mau_epll. The system hang on disabling
> unused clocks from audss block.
> 
> Unfortunately the 'mau_epll' clock is not parent of some of audss clocks.
> 
> Whenever system wants to operate on audss clocks it has to enable epll
> clock. The solution reuses common clk-gate/divider/mux code and duplicates
> clk_register_*() functions.
> 
> Additionally this patch fixes memory leak of clock gate/divider/mux
> structures. The leak exists in generic clk_register_*() functions. Patch
> replaces them with custom code with managed allocation.
> 
> Signed-off-by: Krzysztof Kozlowski <[email-masked]>
> Reported-by: Javier Martinez Canillas <[email-masked]>
> Reported-by: Kevin Hilman <[email-masked]>
> Tested-by: Javier Martinez Canillas <[email-masked]>

Can you confirm sound works with this patch on exynos5420 ? Or does
your Tested-by refer only to successful booting ?

--
Thanks,
Sylwester