Subject: [PATCHv3 2/8] devfreq: exynos: Add documentation for generic exynos memory bus frequency driver

From: [email-masked] (Chanwoo Choi)
Date: Tue, 20 Jan 2015 20:37:52 +0900

On 01/20/2015 08:22 PM, Viresh Kumar wrote:
> On 20 January 2015 at 13:53, Chanwoo Choi <[email-masked]> wrote:
>> But, the frequency of OPPs is only used for devfreq ondemand governor.
>> After deciding the proper frequency of memory bus on ondemand governor,
>> exynos-bus.c (exynos memory bus frequency driver) use the frequency table
>> of memory bus blocks on below to change the clock rate of memory bus block.
> 
>> Firs of all,
>> I explain the hierarchy of Exynos memory buses.
>>
>> For example of Exynos3250 memory bus,
>> This patch divide the memory bus group according to power rail (regulator).
>> - MIF (Memory Interface ) memory bus group uses the VDD_MIF regulator.
>> - INT (Internal) memory bus group uses the VDD_INT regulator.
>>
>> Each memory bus group contains only one power rail(regulator) and one more memory bus blocks as follwing:
>>
>> - MIF memory bus group
>> power rail(VDD_MIF)-->|--- memory bus for DMC (Dynamic Memory Controller) block (dmc clock)
>>
>> - INT memory bus group
>>                       |--- memory bus for PERI block (aclk_100 clock)
>>                       |
>>                       |--- memory bus for DISPLAY block (aclk_160 clock)
>>                       |
>>                       |--- memory bus for ISP block (aclk_200 clock)
>>                       |
>>                       |--- memory bus for GPS block (aclk_266 clock)
>> power rail(VDD_INT)-->|
>>                       |--- memory bus for MCUISP block (aclk_400_mcuisp clock)
>>                       |
>>                       |--- memory bus for Leftbus block (gdl clock)
>>                       |
>>                       |--- memory bus for Rightbus block (gdr clock)
>>                       |
>>                       |--- memory bus for MFC block (mfc clock)
>>
>>
>> Exynos3250 has following table for INT memory bus group:
>> All clocks of INT memory bus group have to contain the same entry count
>> againt the number of 'virtual freqw'. So, each memory bus clock could have duplicate clocks.
>>
>> ------------------------------------------------------------------------
>> Level|virtual freq|PERI's clk|Display's clk|ISP's clk|GPS's clk| voltage|
>> ------------------------------------------------------------------------
>> L6   |400000      |100000    |200000       |200000   |300000   | 95000  |
>> L5   |200000      |100000    |160000       |200000   |200000   | 95000  |
>> L4   |133000      |100000    |100000       |100000   |133000   | 92500  |
>> L3   |100000      |100000    |80000        |80000    |100000   | 85000  |
>> L2   |80000       |50000     |80000        |50000    |50000    | 85000  |
>> L1   |50000       |50000     |50000        |50000    |50000    | 85000  |
>> -------------------------------------------------------------------------
>> (Except for mcuisp, leftbus, rightbus, mfc block)
>>
>> This table is used for devfreq ondemand governor as following:
>> 1. ondemand governor in devfreq use the 'virtual freq' to devcide the proper
>>    frequency for memory bus.
>> 2. ondemand governor executes the *_target() function to set clock rate and voltage.
>> 3. *_target() function in exynos-bus.c changes the clock rate of {PERIS|Display|ISP|GPS} clk
>>    according to decided 'Level' by devfreq ondemand governor.
> 
> I see..
> 
> Please confirm if my understanding is correct.
> - mem-bus-group: all blocks sharing a regulator
> - mem-bus-block: individual blocks managing their clock rate

Right and mem-bus-blcoks are included in a mem-bus-group.

> 
> What you do in kernel is register group as a device (with virtual OPPs)
> and then manage blocks within the driver. And so you need to do this
> dummy mapping of virtual to physical frequencies.

Right.

> 
> It *may* not have done it this way, if I was to design this driver.
> 
> Each bus-block is a separately controllable device and so must be registered
> separately. In that case all bus-blocks will have separate OPP tables and
> all this dummy-v2p mapping will go away.

If each bus-block has separate regulator independently, each bus-block can be registered
separately. But, exynos bus-blocks in mem-bus-group share the same regulator.

> 
> I believe that you are over complicating stuff without any need..
> 
> --
> viresh
> 

Best Regards,
Chanwoo Choi