Subject: [PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain

From: [email-masked] (Sylwester Nawrocki)
Date: Tue, 20 Jan 2015 15:04:00 +0100

Hi,

On 20/01/15 11:35, Javier Martinez Canillas wrote:
> When a power domain is powered off on Exynos5420 SoC, the input clocks of
> the devices attached to this power domain are re-parented to oscclk and
> restored to the original parent after powering on the power domain.
> 
> So a reference to the input and parent clocks for the devices attached to
> a power domain are needed to be able to do the re-parenting. The DISP1 pd
> includes modules which uses the following clocks:
> 
> ACLK_200_DISP1 (MIXER and HDMILINK)
> ACLK_300_DISP1 (FIMD1)
> ACLK_400_DISP1 (Internal Buses)
> 
> Each of these clocks are generated as the output of a clock mux so add an
> ID for all of these clock muxes and their parents to be referenced in the
> DISP1 power domain device node.
> 
> Signed-off-by: Javier Martinez Canillas <[email-masked]>

The patch looks OK to me, I'm fine with it being merged via Kukjin's tree
due to the dts dependencies (including other pending dts patches touching
the arch/arm/boot/dts/exynos5420.dtsi file).
I think we need also Mike ACK for that, I could also queue the patch for
the clk tree and create a topic branch, but merging both patches via
arm-soc seems a more sane option in this case.

Acked-by: Sylwester Nawrocki <[email-masked]>

--
Thanks,
Sylwester