Subject: [RESEND PATCH 2/2] arm: socfpga: Set share override bit of the l2 cache controller

From: [email-masked] (Dinh Nguyen)
Date: Fri, 20 Feb 2015 01:15:21 -0600

Hi Rob,

On 2/19/15 12:13 PM, Rob Herring wrote:
> On Thu, Feb 19, 2015 at 11:06 AM,  <[email-masked]> wrote:
>> From: Dinh Nguyen <[email-masked]>
>>
>> By not having bit 22 set in the PL310 Auxiliary Control register (shared
>> attribute override enable) has the side effect of transforming Normal
>> Shared Non-cacheable reads into Cacheable no-allocate reads.
>>
>> Coherent DMA buffers in Linux always have a Cacheable alias via the
>> kernel linear mapping and the processor can speculatively load cache
>> lines into the PL310 controller. With bit 22 cleared, Non-cacheable
>> reads would unexpectedly hit such cache lines leading to buffer
>> corruption.
> 
> You really should be doing this in your bootloader.
> 

Can I ask what is your reasoning for doing this in the bootloader? It's
seems like this is such a nice mechanism to do it here.

Dinh