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From: jh80.chung@samsung•com (Jaehoon Chung)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH V5 1/2] mmc: dw_mmc: exynos: Support eMMC's HS400 mode
Date: Thu, 26 Feb 2015 10:22:28 +0900	[thread overview]
Message-ID: <54EE7554.6060506@samsung.com> (raw)
In-Reply-To: <CAL_Jsq+Mr=WOoCjWRnHnUqo8+UmqxxHbMG3M8+kLNgfhPASteA@mail.gmail.com>

Dear, Rob.

On 02/25/2015 11:38 PM, Rob Herring wrote:
> On Wed, Jan 28, 2015 at 8:41 PM, Alim Akhtar <alim.akhtar@samsung•com> wrote:
>> From: Seungwon Jeon <tgih.jun@samsung•com>
>>
>> Implements HS400 mode support for exynos host driver.
>> This also include some updates as new mode is added.
>>
>> Signed-off-by: Seungwon Jeon <tgih.jun@samsung•com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung•com>
>> [Alim: addressed review comments]
>> ---
>>  .../devicetree/bindings/mmc/exynos-dw-mshc.txt     |    7 +
>>  drivers/mmc/host/dw_mmc-exynos.c                   |  185 ++++++++++++++++----
>>  drivers/mmc/host/dw_mmc-exynos.h                   |   19 +-
>>  drivers/mmc/host/dw_mmc.c                          |   16 +-
>>  drivers/mmc/host/dw_mmc.h                          |    2 +
>>  5 files changed, 195 insertions(+), 34 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> index ee4fc05..aad9844 100644
>> --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
>> @@ -36,6 +36,8 @@ Required Properties:
>>    in transmit mode and CIU clock phase shift value in receive mode for double
>>    data rate mode operation. Refer notes below for the order of the cells and the
>>    valid values.
>> +* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
>> +  shift value for hs400 mode operation.
> 
> What are the units?

Do you means what is "sumsung,dw-mshci-hs400-timing" unit?
It's timing value for eMMC/SD/SDIO clock phase.(It's exynos specific value.)
Using timing value can shift the H/W clock phase.
If invalid timing value is set, eMMC/SD/SDIO can produce the CRC error.

Do you think it can't include into device-tree?
I want to know your thinking. let me know, plz.

Best Regards,
Jaehoon Chung

> 
> Rob
> 

  reply	other threads:[~2015-02-26  1:22 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-29  2:41 [PATCH v5 0/2] mmc: dw_mmc: exynos: Add HS400 support Alim Akhtar
2015-01-29  2:41 ` [PATCH V5 1/2] mmc: dw_mmc: exynos: Support eMMC's HS400 mode Alim Akhtar
2015-02-25  6:34   ` Jaehoon Chung
2015-02-25  8:12     ` Alim Akhtar
2015-02-25 14:38   ` Rob Herring
2015-02-26  1:22     ` Jaehoon Chung [this message]
2015-01-29  2:41 ` [PATCH V5 2/2] ARM: dts: Add HS400 support for exynos5420 and exynos5800 Alim Akhtar
2015-02-25  6:35   ` Jaehoon Chung
2015-03-15 11:28     ` Alim Akhtar
2015-03-17  2:12       ` Kukjin Kim
2015-03-17 23:26         ` Alim Akhtar
2015-02-06  1:18 ` [PATCH v5 0/2] mmc: dw_mmc: exynos: Add HS400 support Jaehoon Chung
2015-02-06  5:52   ` Vivek Gautam
2015-02-06  6:03     ` Jaehoon Chung
2015-02-06  6:07       ` Vivek Gautam

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