Subject: at91 clocks

From: [email-masked] (Jonas Andersson)
Date: Mon, 30 Mar 2015 13:24:04 +0200

Hi Boris,

On 2015-03-27 15:42, Jonas Andersson wrote:
>
>> Anyway, I don't understand why clk_set_rate returns 0 even when it
>> fails to set the appropriate rate.
>> Could you add some traces in drivers/clk/at91/clk-pll.c
>> (clk_pll_round_rate, clk_pll_set_rate and clk_pll_get_best_div_mul) ?
>
> Yes I'll try to do it on Monday next week.
>
Result and source at http://pastie.org/10062457

Best regards
  Jonas