From: Umang Chheda <umang.chheda@oss•qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss•qualcomm.com>,
Ruidong Tian <tianruidond@linux•alibaba.com>,
Tony Luck <tony.luck@intel•com>, Borislav Petkov <bp@alien8•de>,
Rob Herring <robh@kernel•org>,
Krzysztof Kozlowski <krzk+dt@kernel•org>,
Conor Dooley <conor+dt@kernel•org>,
Bjorn Andersson <andersson@kernel•org>,
Konrad Dybcio <konradybcio@kernel•org>,
catalin.marinas@arm•com, will@kernel•org, lpieralisi@kernel•org,
rafael@kernel•org, mark.rutland@arm•com,
Sudeep Holla <sudeep.holla@kernel•org>
Cc: linux-arm-msm@vger•kernel.org, linux-acpi@vger•kernel.org,
linux-arm-kernel@lists•infradead.org, linux-edac@vger•kernel.org,
linux-kernel@vger•kernel.org, devicetree@vger•kernel.org,
Faruque Ansari <faruque.ansari@oss•qualcomm.com>
Subject: Re: [PATCH 8/8] arm64: dts: qcom: monaco: add AEST error nodes
Date: Wed, 20 May 2026 10:34:19 +0530 [thread overview]
Message-ID: <55470717-3e9e-4548-b12a-8e2a2e1f6c63@oss.qualcomm.com> (raw)
In-Reply-To: <71eee892-1c0b-49e7-a82d-9016c56e8592@oss.qualcomm.com>
On 5/12/2026 4:58 PM, Konrad Dybcio wrote:
> On 5/5/26 2:23 PM, Umang Chheda wrote:
>> Add AEST RAS error source nodes for the Monaco SoC.
>>
>> The DT describes a processor error source covering all CPU cores and a
>> shared L3 cache error source for the cluster. These nodes model the
>> hardware error reporting blocks and associated interrupts as required
>> by the Arm AEST specification.
>>
>> Co-developed-by: Faruque Ansari <faruque.ansari@oss•qualcomm.com>
>> Signed-off-by: Faruque Ansari <faruque.ansari@oss•qualcomm.com>
>> Signed-off-by: Umang Chheda <umang.chheda@oss•qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/monaco.dtsi | 41 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 41 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
>> index 7b1d57460f1e..8e43ceed7d84 100644
>> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
>> @@ -3,6 +3,7 @@
>> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> */
>>
>> +#include <dt-bindings/arm/aest.h>
>> #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
>> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> @@ -29,6 +30,46 @@ / {
>> #address-cells = <2>;
>> #size-cells = <2>;
>>
>> + aest {
>> + compatible = "arm,aest";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>
> These 3 properties aren't necessary if none of the subnodes have a
> 'reg' property
Ack
>
> Konrad
Thanks,
Umang
next prev parent reply other threads:[~2026-05-20 5:04 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-05 12:23 [PATCH 0/8] ras: aest: extend AEST support to Device Tree frontend Umang Chheda
2026-05-05 12:23 ` [PATCH 1/8] ras: aest: Fix shared processor node handling and error log messages Umang Chheda
2026-05-05 12:23 ` [PATCH 2/8] ras: aest: Fix CE/UE error counts not incrementing in debugfs Umang Chheda
2026-05-05 12:23 ` [PATCH 3/8] ras: aest: Skip unimplemented records " Umang Chheda
2026-05-05 12:23 ` [PATCH 4/8] ras: aest: Add panic_on_ue module parameter Umang Chheda
2026-05-06 8:06 ` Ruidong Tian
2026-05-12 6:51 ` Umang Chheda
2026-05-05 12:23 ` [PATCH 5/8] dt-bindings: arm: ras: Introduce bindings for ARM AEST Umang Chheda
2026-05-13 17:58 ` Rob Herring
2026-05-20 18:13 ` Umang Chheda
2026-06-03 10:27 ` Umang Chheda
2026-05-05 12:23 ` [PATCH 6/8] ras: aest: Add DT frontend for ARM AEST RAS error sources Umang Chheda
2026-05-05 12:23 ` [PATCH 7/8] arm64: dts: qcom: lemans: add AEST error nodes Umang Chheda
2026-05-05 12:23 ` [PATCH 8/8] arm64: dts: qcom: monaco: " Umang Chheda
2026-05-12 11:28 ` Konrad Dybcio
2026-05-20 5:04 ` Umang Chheda [this message]
2026-05-06 8:10 ` [PATCH 0/8] ras: aest: extend AEST support to Device Tree frontend Ruidong Tian
2026-05-12 6:45 ` Umang Chheda
2026-05-20 5:54 ` Ruidong Tian
2026-06-02 7:29 ` Ruidong Tian
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