From: vigneshr@ti•com (R, Vignesh)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v2 1/5] ARM: OMAP2+: DRA7: clockdomain: change l4per2_7xx_clkdm to SW_WKUP
Date: Thu, 16 Jul 2015 20:56:54 +0530 [thread overview]
Message-ID: <55A7CD3E.3030803@ti.com> (raw)
In-Reply-To: <alpine.DEB.2.02.1507152020240.32764@utopia.booyaka.com>
Hi,
On 07/16/2015 01:57 AM, Paul Walmsley wrote:
> On Wed, 15 Jul 2015, Paul Walmsley wrote:
>
>> On Wed, 3 Jun 2015, Vignesh R wrote:
>>
>>> Legacy IPs like PWMSS, present under l4per2_7xx_clkdm, cannot support
>>> smart-idle when its clock domain is in HW_AUTO on DRA7 SoCs. Hence,
>>> program clock domain to SW_WKUP.
>>>
>>> Signed-off-by: Vignesh R <vigneshr@ti•com>
>>> ---
>>> arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
>>> index 57d5df0c1fbd..7581e036bda6 100644
>>> --- a/arch/arm/mach-omap2/clockdomains7xx_data.c
>>> +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
>>> @@ -331,7 +331,7 @@ static struct clockdomain l4per2_7xx_clkdm = {
>>> .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
>>> .wkdep_srcs = l4per2_wkup_sleep_deps,
>>> .sleepdep_srcs = l4per2_wkup_sleep_deps,
>>> - .flags = CLKDM_CAN_HWSUP_SWSUP,
>>> + .flags = CLKDM_CAN_SWSUP,
>>> };
>>>
>>> static struct clockdomain mpu0_7xx_clkdm = {
>>
>> Thanks, queued for v4.2-rc fixes. Note that I cannot test this, since I
>> don't have a DRA7xx board.
>
> You know, upon further thought, this doesn't make sense. If the bug
> is with the PWMSS IP block specifically, why not just set
> HWMOD_SWSUP_SIDLE on all the IP blocks where the hardware folks didn't
> implement hardware smart-idle? At least that way, if those legacy IP
> blocks aren't in use, the clockdomain can still enter hardware-supervised
> idle?
According to hardware folks, HW_AUTO (for clockdomain) and
HWMOD_SWSUP_SIDLE (PWMSS in NO-IDLE) for PWMSS *is not* a good
combination. If clockdomain is in HW_AUTO and PWMSS is put in NO-IDLE,
then IDLEST of PWMSSx_CLKCTRL reads "stuck in wakeup/ sleep transition"
which is not a consistent state (this is because of problems with PWM
IP). Hence, it is recommended to program the clock domain to SW_WKUP and
leave the PWMSS idlemode as smart-idle.
--
Regards
Vignesh
next prev parent reply other threads:[~2015-07-16 15:26 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-03 11:51 [PATCH v2 0/5] Add support for PWMSS on DRA7 Vignesh R
2015-06-03 11:51 ` [PATCH v2 1/5] ARM: OMAP2+: DRA7: clockdomain: change l4per2_7xx_clkdm to SW_WKUP Vignesh R
2015-07-15 19:56 ` Paul Walmsley
2015-07-15 20:27 ` Paul Walmsley
2015-07-16 15:26 ` R, Vignesh [this message]
2015-06-03 11:51 ` [PATCH v2 2/5] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS Vignesh R
2015-07-15 21:54 ` Paul Walmsley
2015-07-16 15:31 ` R, Vignesh
2015-07-23 15:35 ` R, Vignesh
2015-07-29 6:32 ` Vignesh R
2015-08-31 15:51 ` Paul Walmsley
2016-02-17 20:42 ` Franklin S Cooper Jr.
2016-02-18 6:58 ` Paul Walmsley
2016-02-18 15:33 ` Franklin S Cooper Jr.
2016-02-18 17:21 ` Paul Walmsley
2015-06-03 11:51 ` [PATCH v2 3/5] ARM: dts: DRA7: Add TBCLK " Vignesh R
2015-06-03 11:51 ` [PATCH v2 4/5] clk: ti: DRA7: Add tbclk data for ehrpwm Vignesh R
2015-06-18 22:39 ` Michael Turquette
2015-06-03 11:51 ` [PATCH v2 5/5] ARM: dts: DRA7: Add dt nodes for PWMSS Vignesh R
2015-07-06 6:11 ` [PATCH v2 0/5] Add support for PWMSS on DRA7 Vignesh R
2015-07-07 12:49 ` Tero Kristo
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