From: zhaoshenglong@huawei•com (Shannon Zhao)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register
Date: Tue, 1 Dec 2015 20:46:29 +0800 [thread overview]
Message-ID: <565D96A5.3000401@huawei.com> (raw)
In-Reply-To: <565D5F2F.1020709@arm.com>
On 2015/12/1 16:49, Marc Zyngier wrote:
> On 01/12/15 01:51, Shannon Zhao wrote:
>> Hi Marc,
>>
>> On 2015/12/1 1:56, Marc Zyngier wrote:
>>> Same remark here as the one I made earlier. I'm pretty sure we don't
>>> call any CP15 reset because they are all shared with their 64bit
>>> counterparts. The same thing goes for the whole series.
>> Ok, I see. But within the 64bit reset function, it needs to update the
>> 32bit register value, right? Since when accessing these 32bit registers,
>> it uses the offset c9_PMXXXX.
>
> It shouldn't, because the 64bit and 32bit share the same storage. From
> your own patch:
>
> +/* Performance Monitors*/
> +#define c9_PMCR (PMCR_EL0 * 2)
> +#define c9_PMOVSSET (PMOVSSET_EL0 * 2)
> +#define c9_PMOVSCLR (PMOVSCLR_EL0 * 2)
> +#define c9_PMCCNTR (PMCCNTR_EL0 * 2)
> +#define c9_PMSELR (PMSELR_EL0 * 2)
> +#define c9_PMCEID0 (PMCEID0_EL0 * 2)
> +#define c9_PMCEID1 (PMCEID1_EL0 * 2)
> +#define c9_PMXEVCNTR (PMXEVCNTR_EL0 * 2)
> +#define c9_PMXEVTYPER (PMXEVTYPER_EL0 * 2)
> +#define c9_PMCNTENSET (PMCNTENSET_EL0 * 2)
> +#define c9_PMCNTENCLR (PMCNTENCLR_EL0 * 2)
> +#define c9_PMINTENSET (PMINTENSET_EL1 * 2)
> +#define c9_PMINTENCLR (PMINTENCLR_EL1 * 2)
> +#define c9_PMUSERENR (PMUSERENR_EL0 * 2)
> +#define c9_PMSWINC (PMSWINC_EL0 * 2)
>
> These are indexes in the copro array:
>
> struct kvm_cpu_context {
> struct kvm_regs gp_regs;
> union {
> u64 sys_regs[NR_SYS_REGS];
> u32 copro[NR_COPRO_REGS];
> };
> };
>
> which is in a union with the sys_reg array. So anything that affects one
> affects the other because:
> - there is only one state in the physical CPU, no matter which mode
> you're in,
> - the guest EL1 is either 32bit or 64bit, and never changes over time.
>
> Hope this helps,
>
Ok, I see. Thanks for the explanation. :)
--
Shannon
next prev parent reply other threads:[~2015-12-01 12:46 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-30 6:21 [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-11-30 18:11 ` Marc Zyngier
2015-10-30 6:21 ` [PATCH v4 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-11-02 20:06 ` Christopher Covington
2015-11-30 17:56 ` Marc Zyngier
2015-12-01 1:51 ` Shannon Zhao
2015-12-01 8:49 ` Marc Zyngier
2015-12-01 12:46 ` Shannon Zhao [this message]
2015-10-30 6:21 ` [PATCH v4 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-11-30 11:42 ` Marc Zyngier
2015-11-30 11:59 ` Shannon Zhao
2015-11-30 13:19 ` Marc Zyngier
2015-10-30 6:21 ` [PATCH v4 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-11-02 20:13 ` Christopher Covington
2015-11-03 2:33 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-11-02 20:54 ` Christopher Covington
2015-11-03 2:41 ` Shannon Zhao
2015-11-30 18:12 ` Marc Zyngier
2015-12-01 2:42 ` Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 09/21] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 10/21] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 11/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 12/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 13/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 14/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 16/21] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-10-30 6:21 ` [PATCH v4 17/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-11-02 21:20 ` Christopher Covington
2015-10-30 6:22 ` [PATCH v4 18/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-10-30 12:08 ` kbuild test robot
2015-10-31 2:06 ` Shannon Zhao
2015-11-30 18:22 ` Marc Zyngier
2015-12-01 14:35 ` Shannon Zhao
2015-12-01 14:50 ` Marc Zyngier
2015-12-01 15:13 ` Shannon Zhao
2015-12-01 15:41 ` Marc Zyngier
2015-12-01 16:26 ` Shannon Zhao
2015-12-01 16:57 ` Marc Zyngier
2015-12-02 2:40 ` Shannon Zhao
2015-12-02 8:45 ` Marc Zyngier
2015-12-02 9:49 ` Shannon Zhao
2015-12-02 10:22 ` Marc Zyngier
2015-12-02 16:27 ` Christoffer Dall
2015-10-30 6:22 ` [PATCH v4 19/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-10-30 6:22 ` [PATCH v4 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-10-30 6:22 ` [PATCH v4 21/21] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-11-30 18:31 ` Marc Zyngier
2015-11-30 18:34 ` [PATCH v4 00/21] KVM: ARM64: Add guest PMU support Marc Zyngier
2015-12-01 1:52 ` Shannon Zhao
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