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From: Suzuki.Poulose@arm•com (Suzuki K. Poulose)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v5 05/11] arm-cci PMU: Delay counter writes to pmu_enable
Date: Tue, 5 Jan 2016 09:59:13 +0000	[thread overview]
Message-ID: <568B93F1.8050202@arm.com> (raw)
In-Reply-To: <20160104192401.GD17127@leverpostej>

On 04/01/16 19:24, Mark Rutland wrote:
> On Mon, Jan 04, 2016 at 11:54:44AM +0000, Suzuki K. Poulose wrote:
>> Delay setting the event periods for enabled events to pmu::pmu_enable().
>> We mark the event.hw->state PERF_HES_ARCH for the events that we know
>> have their counts recorded and have been started.
>
> Please add a comment to the code stating exactly what PERF_HES_ARCH
> means for the CCI PMU driver, so it's easy to find.
>

Sure.

>> +void cci_pmu_update_counters(struct cci_pmu *cci_pmu)
>> +{
>> +	int i;
>> +	unsigned long mask[BITS_TO_LONGS(cci_pmu->num_cntrs)];
>
> I think this can be:
>
> 	DECLARE_BITMAP(mask, cci_pmu->num_cntrs);
>
>> +
>> +	memset(mask, 0, BITS_TO_LONGS(cci_pmu->num_cntrs) * sizeof(unsigned long));
>
> Likewise:
>
> 	bitmap_zero(mask, cci_pmu->num_cntrs);

OK

>> +		if (!cci_pmu->hw_events.events[i]) {
>> +			WARN_ON(1);
>> +			continue;
>> +		}
>> +
>
> 		if (WARN_ON(!cci_pmu->hw_events.events[i]))
> 			continue;

OK
  
>> @@ -980,8 +1015,11 @@ static void cci_pmu_start(struct perf_event *event, int pmu_flags)
>>   	/* Configure the counter unless you are counting a fixed event */
>>   	if (!pmu_fixed_hw_idx(cci_pmu, idx))
>>   		pmu_set_event(cci_pmu, idx, hwc->config_base);
>> -
>> -	pmu_event_set_period(event);
>> +	/*
>> +	 * Mark this counter, so that we can program the
>> +	 * counter with the event_period. see cci_pmu_enable()
>> +	 */
>> +	hwc->state = PERF_HES_ARCH;
>
> Why couldn't we have kept pmu_event_set_period here, and have that set
> prev_count and PERF_HES_ARCH?
>
> Then we'd be able to do the same betching for overflow too.

The pmu is not disabled while we are in overflow irq handler. Hence there may
not be a pmu_enable() which would set the period for the counter which
overflowed, if defer the write in that case. Is that assumption wrong ?

Cheers
Suzuki

  reply	other threads:[~2016-01-05  9:59 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-04 11:54 [PATCH v5 00/11] arm-cci: PMU updates Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 01/11] arm-cci: Define CCI counter period Suzuki K. Poulose
2016-01-04 18:27   ` Mark Rutland
2016-01-05  9:50     ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 02/11] arm-cci: Refactor pmu_write_counter Suzuki K. Poulose
2016-01-04 19:01   ` Mark Rutland
2016-01-04 11:54 ` [PATCH v5 03/11] arm-cci: Group writes to counter Suzuki K. Poulose
2016-01-04 19:03   ` Mark Rutland
2016-01-05 10:51     ` Suzuki K. Poulose
2016-01-11 10:44       ` Mark Rutland
2016-01-11 10:48         ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 04/11] arm-cci: Refactor CCI PMU enable/disable methods Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 05/11] arm-cci PMU: Delay counter writes to pmu_enable Suzuki K. Poulose
2016-01-04 19:24   ` Mark Rutland
2016-01-05  9:59     ` Suzuki K. Poulose [this message]
2016-01-11 10:46       ` Mark Rutland
2016-01-11 11:08         ` Suzuki K. Poulose
2016-01-11 11:24           ` Mark Rutland
2016-01-11 18:12             ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 06/11] arm-cci: Get the status of a counter Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 07/11] arm-cci: Add routines to save/restore all counters Suzuki K. Poulose
2016-01-11 10:50   ` Mark Rutland
2016-01-11 10:58     ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 08/11] arm-cci: Provide hook for writing to PMU counters Suzuki K. Poulose
2016-01-11 10:54   ` Mark Rutland
2016-01-11 12:14     ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 09/11] arm-cci: CCI-500: Work around PMU counter writes Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 10/11] arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 11/11] arm-cci: CoreLink CCI-550 PMU driver Suzuki K. Poulose

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