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From: Suzuki.Poulose@arm•com (Suzuki K Poulose)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 1/3] arm64: dts: juno: add coresight support
Date: Tue, 21 Jun 2016 09:44:28 +0100	[thread overview]
Message-ID: <5768FE6C.3080809@arm.com> (raw)
In-Reply-To: <CAOesGMjQNEOcmYpUAxUxBJLyUYZQuRKK48a31Ys9LuTJFWqMFA@mail.gmail.com>

On 21/06/16 06:41, Olof Johansson wrote:

Hi Olof,


>> +       /*
>> +        * Juno TRMs specify the size for these coresight components as 64K.
>> +        * The actual size is just 4K though 64K is reserved. Access to the
>> +        * unmapped reserved region results in a DECERR response.
>> +        */
>> +       etf at 20010000 {
>


> Would it make sense to name it something like trace-fifo instead? We
> normally name the nodes based on type of device (ethernet@, pci@,
> etc).

ETF (Embedded Trace FIFO) is one of the modes[1] in which you can configure
the Coresight TMC at integration time. The other available modes are
ETR(Embedded Trace Router) and ETB(Embedded Trace Buffer).

>
>
>> +               compatible = "arm,coresight-tmc", "arm,primecell";
>
> Is there a more specific compatible needed here, or does
> arm,coresight-tmc give you all the information you need on how to use
> this interface?

The coresight TMC driver will read the "configured mode" to determine
the mode of operation and initialise it accordingly. Hence we don't
need a specific compatible.

>
> The bindings doc is sort of sparse in this area, all it says is "you
> might use one of these compatibles".

I agree.

>
>> +       tpiu at 20030000 {
>
> Again, these names are not great. Luckily they don't affect the
> binding, so they can be fixed. What would be a more human readable and
> functionally describing name here?

Again, TPIU (Trace Port Interface Unit), is standard Coresight component in
Coresight architecture. [2]


>> +
>> +       etr at 20070000 {
>
> Again..
>

Same as ETF [1]

>> +
>> +       etm0: etm at 22040000 {
>
> If this file is sorted on reg values, then this node and the two after
> are out of order.

They are numbered after the CPU which they are associated with. This is used
to reuse the dts for Juno-r0/r1 vs r2 (where we have A72 replacing A57).


[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0461b/CACECIII.html
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Babhdhfb.html


Cheers
Suzuki

  reply	other threads:[~2016-06-21  8:44 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-06 15:59 [PATCH 0/3] arm64: dts: juno: add coresight support Sudeep Holla
2016-06-06 15:59 ` [PATCH 1/3] " Sudeep Holla
2016-06-08 16:04   ` Liviu Dudau
2016-06-12 21:57   ` Mathieu Poirier
2016-06-13  3:05     ` Mathieu Poirier
2016-06-13  9:18     ` Sudeep Holla
2016-06-13 14:47       ` Mathieu Poirier
2016-06-13 14:53         ` Sudeep Holla
2016-06-17 15:29   ` Mathieu Poirier
2016-06-17 15:33     ` Sudeep Holla
2016-06-21  5:41   ` Olof Johansson
2016-06-21  8:44     ` Suzuki K Poulose [this message]
2016-06-21 11:27     ` Sudeep Holla
2016-06-21 16:30       ` Mathieu Poirier
2016-06-28 17:03       ` Sudeep Holla
2016-06-06 15:59 ` [PATCH 2/3] arm64: dts: juno: add arm,primecell-periphid override Sudeep Holla
2016-06-08 16:05   ` [PATCH 2/3] arm64: dts: juno: add arm, primecell-periphid override Liviu Dudau
2016-06-16 14:42   ` Sudeep Holla
2016-06-06 15:59 ` [PATCH 3/3] arm64: dts: juno: add SCPI power domains for device power management Sudeep Holla
2016-06-08 16:05   ` Liviu Dudau
2016-06-17 15:30   ` Mathieu Poirier
2016-07-06 10:15 ` [PATCH v2 0/2] arm64: dts: juno: add coresight support Sudeep Holla
2016-07-06 10:15   ` [PATCH v2 1/2] " Sudeep Holla
2016-07-06 10:15   ` [PATCH v2 2/2] arm64: dts: juno: add SCPI power domains for device power management Sudeep Holla

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