From: zhengxing@rock-chips•com (Xing Zheng)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq
Date: Wed, 3 Aug 2016 09:25:45 +0800 [thread overview]
Message-ID: <57A14819.9060309@rock-chips.com> (raw)
In-Reply-To: <CAD=FV=X1ZAhzBrFukvE9BxdFmgo8dj4GKjZ9EmPLTagHfO-ufg@mail.gmail.com>
Hi Doug,
On 2016?08?03? 08:49, Doug Anderson wrote:
> Xing,
>
> On Tue, Aug 2, 2016 at 6:13 AM, Xing Zheng <zhengxing@rock-chips•com> wrote:
>> From: Elaine Zhang <zhangqing@rock-chips•com>
>>
>> The suggestion that is from IC designer, the correct pll sequence setting
>> should be like these:
>> ----
>> set pll to slow mode or other plls
>> set pll down
>> set pll params
>> set pll up
>> wait pll lock status
>> set pll to normal mode
>> ----
>>
>> Hence, there are potential risks that we need to fix:
>> rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock
>> rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old params
> I still don't understand how that groks with the statement in the TRM:
>
>> In most cases the PLL programming can be changed on-the-fly and the PLL will simply slew to the new frequency
> That makes it sound like these PLLs are super great at dynamic updates.
>
>
Well, I will report it to IC & Doc folkers to update the TRM and make it
clear.
Thanks.
--
- Xing Zheng
prev parent reply other threads:[~2016-08-03 1:25 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-02 13:13 [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq Xing Zheng
2016-08-03 0:49 ` Doug Anderson
2016-08-03 1:25 ` Xing Zheng [this message]
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