Subject: [PATCH v2 2/2] arm64: dts: Fix broken architected timer interrupt trigger

From: [email-masked] (Marc Zyngier)
Date: Mon, 22 Aug 2016 11:26:33 +0100

Arnd, Olof,

On 01/08/16 10:54, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
> 
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
> 
> The respective maintainers are of course welcome to prove me wrong.
> 
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
> 
> Acked-by: Duc Dang <[email-masked]>
> Acked-by: Carlo Caione <[email-masked]>
> Acked-by: Michal Simek <[email-masked]>
> Acked-by: Krzysztof Kozlowski <[email-masked]>
> Acked-by: Dinh Nguyen <[email-masked]>
> Signed-off-by: Marc Zyngier <[email-masked]>

Any update on this patch? We have a workaround merged already, but it'd
be good to have the DTS fixed as well.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...