Subject: [RFC PATCH 08/11] pci: controller: dra7xx: Add EP mode support

From: [email-masked] (Kishon Vijay Abraham I)
Date: Tue, 27 Sep 2016 17:04:58 +0530

Hi,

On Friday 23 September 2016 08:22 PM, Rob Herring wrote:
> On Wed, Sep 14, 2016 at 10:42:04AM +0530, Kishon Vijay Abraham I wrote:
>> The PCIe controller integrated in dra7xx SoCs is capable of operating
>> in endpoint mode. Add support for dra7xx SoCs to operate in endpoint
>> mode.
>>
>> Signed-off-by: Kishon Vijay Abraham I <[email-masked]>
>> ---
>>  Documentation/devicetree/bindings/pci/ti-pci.txt |   30 ++-
>>  drivers/pci/controller/Kconfig                   |   21 +++
>>  drivers/pci/controller/pci-dra7xx.c              |  211 +++++++++++++++++++---
>>  3 files changed, 225 insertions(+), 37 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> index 60e2516..b0e76f6 100644
>> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
>> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> @@ -1,17 +1,22 @@
>>  TI PCI Controllers
>>  
>>  PCIe Designware Controller
>> - - compatible: Should be "ti,dra7-pcie""
>> - - reg : Two register ranges as listed in the reg-names property
>> - - reg-names : The first entry must be "ti-conf" for the TI specific registers
>> -	       The second entry must be "rc-dbics" for the designware pcie
>> -	       registers
>> -	       The third entry must be "config" for the PCIe configuration space
>> + - compatible: Should be "ti,dra7-pcie" for RC
>> +	       Should be "ti,dra7-pcie-ep" for EP
>>   - phys : list of PHY specifiers (used by generic PHY framework)
>>   - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
>>  	       number of PHYs as specified in *phys* property.
>>   - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
>>  	       where <X> is the instance number of the pcie from the HW spec.
>> + - num-lanes as specified in ../designware-pcie.txt
>> +
>> +HOST MODE
>> +=========
>> + - reg : Two register ranges as listed in the reg-names property
>> + - reg-names : The first entry must be "ti-conf" for the TI specific registers
>> +	       The second entry must be "rc-dbics" for the designware pcie
>> +	       registers
>> +	       The third entry must be "config" for the PCIe configuration space
>>   - interrupts : Two interrupt entries must be specified. The first one is for
>>  		main interrupt line and the second for MSI interrupt line.
>>   - #address-cells,
>> @@ -19,13 +24,24 @@ PCIe Designware Controller
>>     #interrupt-cells,
>>     device_type,
>>     ranges,
>> -   num-lanes,
>>     interrupt-map-mask,
>>     interrupt-map : as specified in ../designware-pcie.txt
>>  
>>  Optional Property:
>>   - gpios : Should be added if a gpio line is required to drive PERST# line
> 
> Don't you need gpios as the input side of GPIO outputs in RC mode? Or 
> for EP mode they are all handled by h/w?

I couldn't find any mention of the gpios being used in EP mode. I'll check this
again.

Thanks
Kishon