From: s.trumtrar@pengutronix•de (Steffen Trumtrar)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v2 1/2] ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges
Date: Fri, 26 Oct 2018 14:43:25 +0200 [thread overview]
Message-ID: <73r2gcnaj6.fsf@pengutronix.de> (raw)
In-Reply-To: <73ftyceiny.fsf@pengutronix.de>
Hi!
Steffen Trumtrar <s.trumtrar@pengutronix•de> writes:
> Hi!
>
> Alan Tull <atull@kernel•org> writes:
>
>> On Thu, Sep 13, 2018 at 2:27 AM Steffen Trumtrar
>> <s.trumtrar@pengutronix•de> wrote:
>>>
>>>
>>> Hi!
>>>
>>> Steffen Trumtrar <s.trumtrar@pengutronix•de> writes:
>>>
>>> > Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs.
>>> >
>>> > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix•de>
>>> > ---
>>> > Changes in v2:
>>> > - set status to disabled, so there are no accidental users
>>> > > of
>>> > the bridges
>>> >
>>> > arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++
>>> > 1 file changed, 14 insertions(+)
>>> >
>>> > diff --git a/arch/arm/boot/dts/socfpga.dtsi
>>> > b/arch/arm/boot/dts/socfpga.dtsi
>>> > index b38f8c240558..11781f795de2 100644
>>> > --- a/arch/arm/boot/dts/socfpga.dtsi
>>> > +++ b/arch/arm/boot/dts/socfpga.dtsi
>>> > @@ -543,6 +543,20 @@
>>> > clocks = <&l4_main_clk>;
>>> > };
>>> >
>>> > + fpga_bridge2: fpga-bridge at ff600000 {
>>> > + compatible =
>>> > "altr,socfpga-fpga2hps-bridge";
>>> > + reg = <0xff600000 0x100000>;
>>> > + resets = <&rst FPGA2HPS_RESET>;
>>> > + clocks = <&l4_main_clk>;
>>> > + status = "disabled";
>>> > + };
>>> > +
>>> > + fpga_bridge3: fpga-bridge at ffc25080 {
>>> > + compatible =
>>> > "altr,socfpga-fpga2sdram-bridge";
>>> > + reg = <0xffc25080 0x4>;
>>> > + status = "disabled";
>>> > + };
>>> > +
>>> > fpgamgr0: fpgamgr at ff706000 {
>>> > compatible = "altr,socfpga-fpga-mgr";
>>> > reg = <0xff706000 0x1000
>>>
>>> Any opinion on this? There shouldn't be any accidental use of
>>> the
>>> bridges now with status=disabled.
>>
>> Hi Steffen,
>>
>> Do you have a use case you need this for?
>>
>
> Yes, of course. I think all our SoCFPGA customers use these
> bridges.
>
>> I don't mind leaving it that way it is and letting people who
>> are
>> actually enabling the bridges in their designs add the whole
>> node.
>>
>
> Why do you think, that these bridges are different from the
> other ones?
> Or other IP blocks on the SoCFPGA even?
> This is the socfpga.dtsi file, it describes the hardware common
> to all
> Cyclone5 SoCs. All SoCs have these bridges, so why not add it?
>
Any opinion on this? I still don't see why these bridges are
different from the other IP cores.
Best regards,
Steffen
--
Pengutronix e.K. | Steffen Trumtrar
|
Industrial Linux Solutions |
http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany| Phone:
+49-5121-206917-0 |
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+49-5121-206917-5555|
prev parent reply other threads:[~2018-10-26 12:43 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-22 8:41 [PATCH v2 1/2] ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges Steffen Trumtrar
2018-08-22 8:41 ` [PATCH v2 2/2] ARM: dts: socfgpa: set bridges status to disabled Steffen Trumtrar
2018-09-13 7:27 ` [PATCH v2 1/2] ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges Steffen Trumtrar
2018-09-13 20:14 ` Alan Tull
2018-09-14 5:45 ` Steffen Trumtrar
2018-10-26 12:43 ` Steffen Trumtrar [this message]
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