Subject: [PATCH v2] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start

From: [email-masked] (Kevin Hilman)
Date: Mon, 09 Jun 2014 11:09:02 -0700

Doug Anderson <[email-masked]> writes:

> On exynos mcpm systems the firmware is hardcoded to jump to an address
> in SRAM (0x02073000) when secondary CPUs come up.  By default the
> firmware puts a bunch of code at that location.  That code expects the
> kernel to fill in a few slots with addresses that it uses to jump back
> to the kernel's entry point for secondary CPUs.
>
> Originally (on prerelease hardware) this firmware code contained a
> bunch of workarounds to deal with boot ROM bugs.  However on all
> shipped hardware we simply use this code to redirect to a kernel
> function for bringing up the CPUs.
>
> Let's stop relying on the code provided by the bootloader and just
> plumb in our own (simple) code jump to the kernel.  This has the nice
> benefit of fixing problems due to the fact that older bootloaders
> (like the one shipped on the Samsung Chromebook 2) might have put
> slightly different code into this location.
>
> Once suspend/resume is implemented for systems using exynos-mcpm we'll
> need to make sure we reinstall our fixed up code after resume.  ...but
> that's not anything new since IRAM (and thus the address of the
> mcpm_entry_point) is lost across suspend/resume anyway.
>
> Signed-off-by: Doug Anderson <[email-masked]>

Acked-by: Kevin Hilman <[email-masked]>
Tested-by: Kevin Hilman <[email-masked]>

I confirm that this patch (plus the enable CCI hack[1]) allows me to see
all 8 cores when booting linux-next on my Chromebook2.

Kevin

[1] While waiting for the forth-coming patch from Andrew to enable the
    CCI port for the boot cluster), I do this from u-boot before starting
    the kernel (based on earlier email from Doug):

    mw.l 10d25000 3  # Enable CCI from U-Boot