From: Sascha Bischoff <Sascha.Bischoff@arm•com>
To: "maz@kernel•org" <maz@kernel•org>
Cc: "yuzenghui@huawei•com" <yuzenghui@huawei•com>,
Timothy Hayes <Timothy.Hayes@arm•com>,
Suzuki Poulose <Suzuki.Poulose@arm•com>, nd <nd@arm•com>,
"peter.maydell@linaro•org" <peter.maydell@linaro•org>,
"kvmarm@lists•linux.dev" <kvmarm@lists•linux.dev>,
"linux-arm-kernel@lists•infradead.org"
<linux-arm-kernel@lists•infradead.org>,
"kvm@vger•kernel.org" <kvm@vger•kernel.org>,
Joey Gouly <Joey.Gouly@arm•com>,
"lpieralisi@kernel•org" <lpieralisi@kernel•org>,
"oliver.upton@linux•dev" <oliver.upton@linux•dev>
Subject: Re: [PATCH v2 03/39] irqchip/gic-v5: Setup gic_kvm_info on ACPI hosts
Date: Fri, 29 May 2026 14:33:57 +0000 [thread overview]
Message-ID: <86ce9d751635eb6cd1c39db8d5501829851641e5.camel@arm.com> (raw)
In-Reply-To: <86mrxlunue.wl-maz@kernel.org>
On Wed, 2026-05-27 at 11:51 +0100, Marc Zyngier wrote:
> On Thu, 21 May 2026 15:50:09 +0100,
> Sascha Bischoff <Sascha.Bischoff@arm•com> wrote:
> >
> > Device-tree based GICv5 probing already passes the IRS details and
> > maintenance interrupt to KVM, but the ACPI path only initialises
> > the
> > irqchip and installs the ACPI IRQ model. As a result, KVM never
> > sees
> > the GICv5 host information required to probe the vGIC on ACPI
> > systems.
> >
> > Add the ACPI equivalent of the DT KVM setup. Parse the MADT GICC
> > entries for the maintenance interrupt, require all relevant entries
> > to
> > agree, register the interrupt as a GICv5 PPI-encoded GSI, and pass
> > the
> > resulting IRQ together with the IRS base and coherency information
> > to
> > KVM. Native GICv5 does not require a maintenance interrupt unless
> > the
> > legacy GICv3-compatible CPU interface is present, so preserve the
> > existing no-maintenance-IRQ handling for that case.
> >
> > Signed-off-by: Sascha Bischoff <sascha.bischoff@arm•com>
> > ---
> > drivers/irqchip/irq-gic-v5.c | 103
> > +++++++++++++++++++++++++++++++++--
> > 1 file changed, 98 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-
> > gic-v5.c
> > index 707deabbf2f63..ccd1ec69a6ab2 100644
> > --- a/drivers/irqchip/irq-gic-v5.c
> > +++ b/drivers/irqchip/irq-gic-v5.c
> > @@ -1126,7 +1126,7 @@ static void gicv5_set_cpuif_idbits(void)
> > #ifdef CONFIG_KVM
> > static struct gic_kvm_info gic_v5_kvm_info __initdata;
> >
> > -static void __init gic_of_setup_kvm_info(struct device_node *node)
> > +static void __init gic_setup_kvm_info(unsigned int maint_irq)
> > {
> > struct gicv5_irs_chip_data *irs_data =
> > gicv5_irs_get_chip_data();
> >
> > @@ -1140,13 +1140,14 @@ static void __init
> > gic_of_setup_kvm_info(struct device_node *node)
> > return;
> > }
> >
> > - gic_v5_kvm_info.type = GIC_V5;
> > + if (WARN_ON(!irs_data))
> > + return;
> >
> > + gic_v5_kvm_info.type = GIC_V5;
> > gic_v5_kvm_info.gicv5_irs.base = irs_data->irs_base;
> > gic_v5_kvm_info.gicv5_irs.non_coherent = !!(irs_data-
> > >flags & IRS_FLAGS_NON_COHERENT);
> > -
> > - /* GIC Virtual CPU interface maintenance interrupt */
> > - gic_v5_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
> > + gic_v5_kvm_info.maint_irq = maint_irq;
> > + gic_v5_kvm_info.no_maint_irq_mask = false;
>
>
> You remove this last line from patch #1, and reintroduce it here. My
> gut feeling is that it should never be removed the first place.
Agreed. I've cleaned that noise up.
>
> >
> > /*
> > * We require an MI if we have legacy support, but don't,
> > otherwise.
> > @@ -1162,10 +1163,101 @@ static void __init
> > gic_of_setup_kvm_info(struct device_node *node)
> >
> > vgic_set_kvm_info(&gic_v5_kvm_info);
> > }
> > +
> > +static void __init gic_of_setup_kvm_info(struct device_node *node)
> > +{
> > + /* GIC Virtual CPU interface maintenance interrupt */
> > + gic_setup_kvm_info(irq_of_parse_and_map(node, 0));
> > +}
> > +
> > +#ifdef CONFIG_ACPI
> > +struct gicv5_acpi_kvm_info {
> > + u32 maint_irq;
> > + int maint_irq_mode;
> > +};
> > +
> > +static struct gicv5_acpi_kvm_info acpi_v5_kvm_info __initdata;
> > +
> > +static int __init gic_acpi_parse_virt_madt_gicc(union
> > acpi_subtable_headers *header,
> > + const unsigned
> > long end)
> > +{
> > + struct acpi_madt_generic_interrupt *gicc =
> > + (struct acpi_madt_generic_interrupt *)header;
> > + static int first_madt = true;
> > + int maint_irq_mode;
> > +
> > + if (!(gicc->flags &
> > + (ACPI_MADT_ENABLED |
> > ACPI_MADT_GICC_ONLINE_CAPABLE)))
> > + return 0;
> > +
> > + maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
> > + ACPI_EDGE_SENSITIVE :
> > ACPI_LEVEL_SENSITIVE;
> > +
> > + if (first_madt) {
> > + first_madt = false;
> > +
> > + acpi_v5_kvm_info.maint_irq = gicc->vgic_interrupt;
> > + acpi_v5_kvm_info.maint_irq_mode = maint_irq_mode;
> > + return 0;
> > + }
> > +
> > + /* The maintenance interrupt must be the same for every
> > GICC entry. */
> > + if (acpi_v5_kvm_info.maint_irq != gicc->vgic_interrupt ||
> > + acpi_v5_kvm_info.maint_irq_mode != maint_irq_mode)
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
> > +static bool __init gic_acpi_collect_virt_info(void)
> > +{
> > + int count;
> > +
> > + acpi_v5_kvm_info.maint_irq = 0;
> > + acpi_v5_kvm_info.maint_irq_mode = 0;
> > +
> > + count =
> > acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
> > +
> > gic_acpi_parse_virt_madt_gicc, 0);
> > +
> > + return count > 0;
> > +}
> > +
> > +static void __init gic_acpi_setup_kvm_info(void)
> > +{
> > + unsigned int maint_irq = 0;
> > + int irq;
> > +
> > + if (!gic_acpi_collect_virt_info()) {
> > + pr_warn("Unable to get hardware information used
> > for virtualization\n");
> > + return;
> > + }
> > +
> > + if (acpi_v5_kvm_info.maint_irq) {
> > + u32 gsi = FIELD_PREP(GICV5_HWIRQ_TYPE,
> > GICV5_HWIRQ_TYPE_PPI) |
> > + FIELD_PREP(GICV5_HWIRQ_ID,
> > acpi_v5_kvm_info.maint_irq);
> > +
> > + irq = acpi_register_gsi(NULL, gsi,
> > + acpi_v5_kvm_info.maint_irq
> > _mode,
> > + ACPI_ACTIVE_HIGH);
> > + if (irq <= 0)
> > + return;
>
> This probably deserves a bit of a warning. And maybe not completely
> fail the registration with KVM?
That's a good point. At this stage we don't know if we have legacy
support or not, which means we also don't know if we need the MI in the
first place. I've changed to emitting a warning here, and let the
existing code in gic_setup_kvm_info() figure out if we can continue or
not.
>
> Thanks,
>
> M.
>
Thanks,
Sascha
next prev parent reply other threads:[~2026-05-29 14:35 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-21 14:49 [PATCH v2 00/39] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-05-21 14:49 ` [PATCH v2 01/39] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-05-21 14:49 ` [PATCH v2 02/39] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-05-21 14:50 ` [PATCH v2 03/39] irqchip/gic-v5: Setup gic_kvm_info on ACPI hosts Sascha Bischoff
2026-05-27 10:51 ` Marc Zyngier
2026-05-29 14:33 ` Sascha Bischoff [this message]
2026-05-28 7:14 ` Lorenzo Pieralisi
2026-05-29 14:41 ` Sascha Bischoff
2026-05-21 14:50 ` [PATCH v2 04/39] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-05-21 14:50 ` [PATCH v2 05/39] arm64/sysreg: Add GICv5 GIC VDPEND and VDRCFG encodings Sascha Bischoff
2026-05-21 14:51 ` [PATCH v2 06/39] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-05-21 14:51 ` [PATCH v2 07/39] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-05-21 14:51 ` [PATCH v2 08/39] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-05-21 14:52 ` [PATCH v2 09/39] KVM: arm64: gic-v5: Create & manage VM and VPE tables Sascha Bischoff
2026-05-21 14:52 ` [PATCH v2 10/39] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-05-21 14:52 ` [PATCH v2 11/39] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-05-21 14:53 ` [PATCH v2 12/39] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-05-21 14:53 ` [PATCH v2 13/39] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-05-21 14:53 ` [PATCH v2 14/39] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-05-21 14:54 ` [PATCH v2 15/39] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-05-21 14:54 ` [PATCH v2 16/39] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-05-21 14:54 ` [PATCH v2 17/39] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-05-21 14:55 ` [PATCH v2 18/39] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-05-21 14:55 ` [PATCH v2 19/39] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-05-21 14:55 ` [PATCH v2 20/39] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-05-21 14:56 ` [PATCH v2 21/39] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-05-21 14:56 ` [PATCH v2 22/39] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-05-21 14:57 ` [PATCH v2 23/39] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-05-21 14:57 ` [PATCH v2 24/39] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-05-21 14:57 ` [PATCH v2 25/39] KVM: arm64: gic-v5: Introduce SPI AP list Sascha Bischoff
2026-05-21 14:58 ` [PATCH v2 26/39] KVM: arm64: gic-v5: Add GIC VDPEND and GIC VDRCFG hyp calls Sascha Bischoff
2026-05-21 14:58 ` [PATCH v2 27/39] KVM: arm64: gic-v5: Track SPI state for in-flight SPIs Sascha Bischoff
2026-05-21 14:58 ` [PATCH v2 28/39] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-05-21 14:59 ` [PATCH v2 29/39] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-05-26 13:41 ` Vladimir Murzin
2026-05-28 14:59 ` Sascha Bischoff
2026-05-21 14:59 ` [PATCH v2 30/39] Documentation: KVM: Extend VGICv5 docs for KVM_VGIC_V5_ADDR_TYPE_IRS Sascha Bischoff
2026-05-21 14:59 ` [PATCH v2 31/39] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-06-04 10:51 ` Vladimir Murzin
2026-05-21 15:00 ` [PATCH v2 32/39] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-05-21 15:00 ` [PATCH v2 33/39] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-05-21 15:00 ` [PATCH v2 34/39] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-05-21 15:01 ` [PATCH v2 35/39] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-05-21 15:01 ` [PATCH v2 36/39] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-05-21 15:01 ` [PATCH v2 37/39] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-05-21 15:02 ` [PATCH v2 38/39] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-05-21 15:02 ` [PATCH v2 39/39] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
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