Subject: Re: [PATCH v1] irqchip: fix mask alignment in gic-v2m

From: Marc Zyngier <[email-masked]>
Date: Mon, 23 Mar 2026 13:37:46 +0000

On Sat, 21 Mar 2026 14:12:16 +0000,
Javier Achirica <[email-masked]> wrote:
> 
> commit 2ef3886ce626dcdab0cbc452dbbebc19f57133d8 ("irqchip/gic-v2m: Handle
> Multiple MSI base IRQ Alignment") introduced a regression in kernel 6.12.58
> affecting PCIe devices using GICv2m MSI on a Qualcomm (arm64) platform.
> 
> It uses nr_irqs parameter to generate a mask to align the MSI base address,
> but this mask isn't properly generated when nr_irqs isn't a power of two.
> This bug was found while adding support for the TCL HH500V router in OpenWrt.
> 
> This patch fixes the issue, can be cleanly applied to the 6.12.x tree and,
> with a small fuzz, to 7.0.x.
> 
> Signed-off-by: Javier Achirica <[email-masked]>
> Cc: [email-masked]
> ---
> --- a/drivers/irqchip/irq-gic-v2m.c     2026-03-20 09:45:22.170192561 +0100
> +++ b/drivers/irqchip/irq-gic-v2m.c     2026-03-20 09:45:26.284210783 +0100
> @@ -158,7 +158,7 @@
>         struct v2m_data *v2m = NULL, *tmp;
>         int hwirq, i, err = 0;
>         unsigned long offset;
> -       unsigned long align_mask = nr_irqs - 1;
> +       unsigned long align_mask = roundup_pow_of_two(nr_irqs) - 1;
> 
>         spin_lock(&v2m_lock);
>         list_for_each_entry(tmp, &v2m_nodes, entry) {
> 

This looks wrong for a bunch of reasons:

- you're hacking the allocation path, but not the free path -- what
  could possibly go wrong?

- nr_irqs not being a power of two to start with is more indicative of
  a bug somewhere else in the system. The only case where we allocate
  more than a single IRQ at a time is for Multi-MSI, and that is
  definitely a power-of-two construct.

I have seen other reports, all concerning QC based HW allocating silly
(aka non Po2) numbers of interrupts for Nulti-MSI devices, and I think
we should instead address the root cause, most likely in the PCI code.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.