Subject: Re: [PATCH 4/8] arm64: dts: add NXP S32G2 support

From: Marc Zyngier <[email-masked]>
Date: Sat, 21 Aug 2021 15:20:30 +0100

On Sat, 21 Aug 2021 13:39:04 +0100,
Chester Lin <[email-masked]> wrote:
> 
> The following log shows that the "Last" bit (GICR_TYPER[4]) of RD at
> 508e0000 has been set.
> 
> localhost:~ # dmesg | grep GIC
> [    0.000000] CPU features: detected: GIC system register CPU interface
> [    0.000000] GICv3: 544 SPIs implemented
> [    0.000000] GICv3: 0 Extended SPIs implemented
> [    0.000000] GICv3: Distributor has no Range Selector support
> [    0.000000] GICv3: 16 PPIs implemented
> [    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000050880000 last: 0
> [    0.078745] GICv3: CPU1: found redistributor 1 region 0:0x00000000508a0000 last: 0
> [    0.089598] GICv3: CPU2: found redistributor 100 region 0:0x00000000508c0000 last: 0
> [    0.100395] GICv3: CPU3: found redistributor 101 region 0:0x00000000508e0000 last: 1

Looks convincing enough. Trimming the RD range to 512kB is then the
right thing to do.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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