Subject: Re: [PATCH] clk: mvebu: armada-37xx-periph: Fix initialization for cpu clocks

From: Gregory CLEMENT <[email-masked]>
Date: Thu, 14 Mar 2019 15:20:37 +0100

Hi Ilias,
 
 On jeu., mars 14 2019, Ilias Apalodimas <[email-masked]> wrote:

> Hello Christian,
>> Hi,
>> 
>> I assume you use the 1000 MHz firmware. This does also not work on my Rev 7
>> board. But I'm pretty sure this is not a problem of the patches, because if
>> I take a newer kernel (4.19.20/27) without the patches it also does not
>> work. A kernel 4.19.17 does work for me. My opinion on that is that this is
>> another problem which does just occure now because now the cpu frequency
>> scaling is working with the right frequencies.
> I am not sure which firmware i am running, i did all my tests on 5.0.0 and
> changing between governors worked fine without the patches

Curently my espressobin is broken so I tested the patches on the Armada
3700 DB and I didn't observe the issue you had.

The 3700 DB I used is configured to run at 800MHz.

Could you apply the following patch and sent me the boot log?

diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 26ed3c18a239..f814ade5cd80 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -452,14 +452,17 @@ static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
 
        /* Set the parent clock for all the load level */
        for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
-               unsigned int reg, mask,  val,
+               unsigned int reg, mask,  val, old,
                        offset = ARMADA_37XX_NB_TBG_SEL_OFF;
 
                armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
 
                val = index << offset;
                mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
+               regmap_read(base, reg, &old);
                regmap_update_bits(base, reg, mask, val);
+               pr_err("%s old=%X -> val=0x%X load_level=%d\n",
+                      __func__, old,  val, load_level);
        }
        return 0;
 }

>
> Regards
> /Ilias
>> 
>> Ilias Apalodimas <[email-masked]> schrieb am Do., 14. März
>> 2019, 13:15:
>> 
>> > Hi Gregory,
>> > > The clock parenting was not setup properly when DVFS was enabled. It was
>> > > expected that the same clock source was used with and without DVFS which
>> > > was not the case.
>> > >
>> > > This patch fixes this issue, allowing to make the cpufreq support work
>> > > when the CPU clocks source are not the default ones.
>> > >
>> > > Fixes: 92ce45fb875d ("cpufreq: Add DVFS support for Armada 37xx")
>> > > Cc: <[email-masked]>
>> > > Reported-by: Christian Neubert <[email-masked]>
>> > > Reported-by: Ilias Apalodimas <[email-masked]>
>> > > Signed-off-by: Gregory CLEMENT <[email-masked]>
>> > > ---
>> > >  drivers/clk/mvebu/armada-37xx-periph.c | 11 +++++++++++
>> > >  1 file changed, 11 insertions(+)
>> > >
>> > > diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
>> > b/drivers/clk/mvebu/armada-37xx-periph.c
>> > > index 1f1cff428d78..26ed3c18a239 100644
>> > > --- a/drivers/clk/mvebu/armada-37xx-periph.c
>> > > +++ b/drivers/clk/mvebu/armada-37xx-periph.c
>> > > @@ -671,6 +671,17 @@ static int armada_3700_add_composite_clk(const
>> > struct clk_periph_data *data,
>> > >               map = syscon_regmap_lookup_by_compatible(
>> > >                               "marvell,armada-3700-nb-pm");
>> > >               pmcpu_clk->nb_pm_base = map;
>> > > +
>> > > +             /*
>> > > +              * Use the same parent when DVFS is enabled that the
>> > > +              * default parent received at boot time. When this
>> > > +              * function is called, DVFS is not enabled yet, so we
>> > > +              * get the default parent and we can set the parent
>> > > +              * for DVFS.
>> > > +              */
>> > > +             if (clk_pm_cpu_set_parent(muxrate_hw,
>> > > +
>> >  clk_pm_cpu_get_parent(muxrate_hw)))
>> > > +                     dev_warn(dev, "Failed to setup default parent
>> > clock for DVFS\n");
>> > >       }
>> > >
>> > >       *hw = clk_hw_register_composite(dev, data->name,
>> > data->parent_names,
>> > > --
>> > > 2.20.1
>> > >
>> > Applied this and selected only
>> >
>> > CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
>> > CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
>> > CONFIG_CPU_FREQ_GOV_POWERSAVE=y
>> >
>> > After changing the governor from 'powersave' to 'performance' the board
>> > completely froze (i even lost access to the serial port)
>> >
>> > Cheers
>> > /Ilias
>> >

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com

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