Subject: Re: Excessive TLB flush ranges

From: Thomas Gleixner <[email-masked]>
Date: Tue, 16 May 2023 21:32:32 +0200

On Tue, May 16 2023 at 10:56, Nadav Amit wrote:
>> On May 16, 2023, at 7:38 AM, Thomas Gleixner <[email-masked]> wrote:
>> 
>> There is a world outside of x86, but even on x86 it's borderline silly
>> to take the whole TLB out when you can flush 3 TLB entries one by one
>> with exactly the same number of IPIs, i.e. _one_. No?
>
> I just want to re-raise points that were made in the past, including in
> the discussion that I sent before and match my experience.
>
> Feel free to reject them, but I think you should not ignore them.

I'm not ignoring them and I'm well aware of these issues. No need to
repeat them over and over. I'm old but not senile yet.

It might turn out that it's not the proper solution for x86, but the
generic vmalloc code as of today is written with an x86 centric view.

That actively hurts other architectures which do have different
constraints than x86. Any architecture which can do IPI-less TLB flushes
seriously wants to decide on their own whether a flush all is the better
option or not. Blindly coalescing random address ranges makes this
impossible as demonstrated.

Aside of that I just wrote the patch for x86 in the first place because
I couldn't be bothered to find and setup an ARM box to test on.

Thanks,

        tglx

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