Subject: [RFT PATCH v4 0/3] usb: dwc2: Fix core reset and force mode delays

From: [email-masked] (Felipe Balbi)
Date: Wed, 07 Sep 2016 13:29:54 +0300

Hi,

Stefan Wahren <[email-masked]> writes:
> Hi John,
>
>> John Youn <[email-masked]> hat am 1. September 2016 um 23:07
>> geschrieben:
>> 
>> 
>> This series accounts for the delay from the IDDIG debounce filter when
>> switching modes. This delay is a function of the PHY clock speed and
>> can range from 5-50 ms. This delay must be taken into account on core
>> reset and force modes. A full explanation is provided in the patch
>> commit log and code comments.
>> 
>> This revision of the series increases the IDDIG delay to 100 ms. Some
>> rockchip platforms seem to timeout even with 50 ms so I have doubled
>> this.
>> 
>> Appreciate any testing on RK3188 and RPi platforms.
>
> i tested the whole series successful with a Raspberry Pi B in dr_mode "host" and
> "otg"
>
> Tested-by: Stefan Wahren <[email-masked]>

John, when you're happy with the series, please resend without RFT so I
can apply :-)

-- 
balbi
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