Subject: Re: Excessive TLB flush ranges

From: Thomas Gleixner <[email-masked]>
Date: Wed, 17 May 2023 13:47:16 +0200

On Wed, May 17 2023 at 12:31, Thomas Gleixner wrote:
> On Tue, May 16 2023 at 18:23, Nadav Amit wrote:
>>> INVLPG is not serializing so the CPU can pull in the next required cache
>>> line(s) on the VA list during that.
>>
>> Indeed, but ChatGPT says (yes, I see you making fun of me already):
>> “however, this doesn't mean INVLPG has no impact on the pipeline. INVLPG
>> can cause a pipeline stall because the TLB entry invalidation must be
>> completed before subsequent instructions that might rely on the TLB can
>> be executed correctly.”
>>
>> So I am not sure that your claim is exactly correct.
>
> Key is a subsequent instruction which might depend on the to be flushed
> TLB entry. That's obvious, but I'm having a hard time to construct that
> dependent intruction in this case.

But obviously a full TLB flush _is_ guaranteed to stall the pipeline,
right?

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