Subject: Re: [PATCH v2 05/10] phy: add A3700 UTMI PHY driver

From: Gregory CLEMENT <[email-masked]>
Date: Fri, 18 Jan 2019 17:36:36 +0100

Hi Miquel,

I have only a few smallish remarks:

 On ven., janv. 11 2019, Miquel Raynal <[email-masked]> wrote:

> Marvell Armada 3700 SoC has two USB controllers, each of them being
> wired to an internal UTMI PHY. Add a driver to control them.
>
> Igal Liberman worked on supporting the PHY, I took the while 'register
> configuration' from his work and rewrote almost entirely the
> driver/bindings around it.
>
> Co-developed-by: Igal Liberman <[email-masked]>
> Signed-off-by: Miquel Raynal <[email-masked]>
> Signed-off-by: Igal Liberman <[email-masked]>
> ---
[...]

> diff --git a/drivers/phy/marvell/phy-mvebu-a3700-utmi.c b/drivers/phy/marvell/phy-mvebu-a3700-utmi.c
> new file mode 100644
> index 000000000000..97d8235d661d
> --- /dev/null
> +++ b/drivers/phy/marvell/phy-mvebu-a3700-utmi.c
> @@ -0,0 +1,297 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 Marvell
> + *
> + * Authors:
> + *   Evan Wang <[email-masked]>
> + *   Miquèl Raynal <[email-masked]>

If it is co-developed with Igal Liberman, shouldn't be added here too?
[...]

> +static int mvebu_a3700_utmi_phy_power_on(struct phy *phy)
> +{
> +	struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy);
> +	struct device *dev = &phy->dev;
> +	int usb32 = utmi->caps->usb32;
> +	int ret = 0;
> +	u32 reg;
> +
> +	if (!utmi)
> +		return -ENODEV;
> +
> +	/*
> +	 * Setup PLL. 40MHz clock used to be the default, bein 25MHz now.
                                                          bein?
> +	 * See "PLL Settings for Typical REFCLK" table.

[...]

> +
> +	/* Wait for squetch calibration */
                    squetch?

Gregory

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com

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