Subject: Re: [PATCH 07/10] clk: amlogic: Support POWER_OF_TWO for PLL pre-divider

From: Jian Hu <[email-masked]>
Date: Wed, 20 May 2026 13:47:27 +0800

On 5/14/2026 11:11 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On lun. 11 mai 2026 at 20:47, Jian Hu via B4 Relay <[email-masked]> wrote:
>
>> From: Jian Hu <[email-masked]>
>>
>> The A9 PLL pre-divider uses a division factor of 2^n to ensure a clock
>> duty cycle of 50% after predivision.
>>
>> Add flag 'CLK_MESON_PLL_N_POWER_OF_TWO' to indicate that the PLL
>> pre-divider division factor is 2^n.
> I understand what you are doing here but I have to ask why this can't be
> implemented with independent dividers that already supports power of 2 ?

If we use independent dividers, the n member would have to be removed 
from meson_clk_pll_data.

However, n is referenced 35 times in clk-pll.c, which means we would 
need to modify all
related logic across the file. This would be a relatively large change.

Moreover, for all Amlogic chips, the n divider is an indispensable part 
of the DCO clock.
The difference between SoC generations is as follows:
     Previous SoCs PLL: n = 1, 2, 3, 4... (linear divider)
     A9 SoC PLL:            n = 2^0, 2^1, 2^2, 2^3, 2^4... (power-of-two 
divider)

Therefore, splitting out the n divider from the DCO clock might not be a 
good design choice.

[...]

Best regards,

Jian