Subject: Re: [PATCH v5 1/8] clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210

From: Dmitry Osipenko <[email-masked]>
Date: Tue, 10 Mar 2020 19:19:59 +0300

10.03.2020 18:19, Thierry Reding пишет:
> From: Joseph Lo <[email-masked]>
> 
> Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
> clock source.
> 
> Signed-off-by: Joseph Lo <[email-masked]>
> Signed-off-by: Thierry Reding <[email-masked]>
> ---
>  drivers/clk/tegra/clk-tegra210.c         | 11 +++++++++++
>  include/dt-bindings/clock/tegra210-car.h |  4 ++--
>  2 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 45d54ead30bc..f99647b4a71f 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -3161,6 +3161,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
>  	clk_register_clkdev(clk, "pll_m_ud", NULL);
>  	clks[TEGRA210_CLK_PLL_M_UD] = clk;
>  
> +	/* PLLMB_UD */
> +	clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb",
> +					CLK_SET_RATE_PARENT, 1, 1);
> +	clk_register_clkdev(clk, "pll_mb_ud", NULL);
> +	clks[TEGRA210_CLK_PLL_MB_UD] = clk;
> +
> +	/* PLLP_UD */
> +	clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p",
> +					0, 1, 1);
> +	clks[TEGRA210_CLK_PLL_P_UD] = clk;

Isn't it possible to auto-enable the low-jitter bit when necessary
during of the rate-change based on a given clock-rate?

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