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From: Andrew Lunn <andrew@lunn•ch>
To: "Russell King (Oracle)" <linux@armlinux•org.uk>
Cc: Corentin Labbe <clabbe.montjoie@gmail•com>,
	linus.walleij@linaro•org, ulli.kroll@googlemail•com,
	kuba@kernel•org, davem@davemloft•net, hkallweit1@gmail•com,
	linux-arm-kernel@lists•infradead.org, netdev@vger•kernel.org,
	linux-kernel@vger•kernel.org
Subject: Re: net: phy: marvell: network working with generic PHY and not with marvell PHY
Date: Tue, 4 Jan 2022 15:46:19 +0100	[thread overview]
Message-ID: <YdRdu3jFPnGd1DsH@lunn.ch> (raw)
In-Reply-To: <YdRZQl6U0y19P/0+@shell.armlinux.org.uk>

> @@ -1227,16 +1227,18 @@ static int m88e1118_config_init(struct phy_device *phydev)
>  {
>  	int err;
>  
> -	/* Change address */
> -	err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
> -	if (err < 0)
> -		return err;
> -
>  	/* Enable 1000 Mbit */
> -	err = phy_write(phydev, 0x15, 0x1070);
> +	err = phy_write_paged(phydev, MII_MARVELL_MSCR_PAGE,
> +			      MII_88E1121_PHY_MSCR_REG, 0x1070);

Ah, yes, keeping this makes it more backwards compatible.

It would be nice to replace the 0x1070 with #defines.

We already have:

#define MII_88E1121_PHY_MSCR_RX_DELAY	BIT(5)
#define MII_88E1121_PHY_MSCR_TX_DELAY	BIT(4)
#define MII_88E1121_PHY_MSCR_DELAY_MASK	(BIT(5) | BIT(4))

Bits 6 is the MSB of the default MAC speed.
Bit 13 is the LSB of the default MAC speed. These two should default to 10b = 1000Mbps
Bit 12 is reserved, and should be written 1.

    Andrew

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  reply	other threads:[~2022-01-04 14:47 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-04 10:58 net: phy: marvell: network working with generic PHY and not with marvell PHY Corentin Labbe
2022-01-04 11:14 ` Russell King (Oracle)
2022-01-04 11:33   ` Corentin Labbe
2022-01-04 11:41     ` Russell King (Oracle)
2022-01-04 12:09       ` Corentin Labbe
2022-01-04 12:17         ` Russell King (Oracle)
2022-01-04 12:11       ` Russell King (Oracle)
2022-01-04 13:57         ` Corentin Labbe
2022-01-04 14:11         ` Corentin Labbe
2022-01-04 14:27           ` Russell King (Oracle)
2022-01-04 14:46             ` Andrew Lunn [this message]
2022-01-04 14:57               ` Russell King (Oracle)
2022-01-04 15:02                 ` Andrew Lunn
2022-01-04 15:04             ` Corentin Labbe
2022-01-04 14:36           ` Andrew Lunn

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