Subject: Re: [PATCH v2] arm: lpae: fix non-atomic page table entry update issue

From: "Russell King (Oracle)" <[email-masked]>
Date: Sun, 15 Mar 2026 01:12:28 +0000

On Sun, Mar 15, 2026 at 08:47:46AM +0800, Wang YanQing wrote:
> The ARM Architecture Reference Manual explicitly dictates that writes of 64-bit
> translation table descriptors must be single-copy atomic:
> ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition (https://developer.arm.com/documentation/ddi0406/latest)
> "
> ...
> A3.5.3 Atomicity in the ARM architecture
> ...
> In an implementation that includes the Large Physical Address Extension, LDRD, and STRD accesses to 64-bit aligned
> locations are 64-bit single-copy atomic as seen by translation table walks and accesses to translation tables.
> Note
> The Large Physical Address Extension adds this requirement to avoid the need for complex measures to avoid
> atomicity issues when changing translation table entries, without creating a requirement that all locations in the
> memory system are 64-bit single-copy atomic.

Thanks. Now, please locate where the need for the updates to the page
tables needs to be done atomically, bearing in mind that we program
SCTLR.AFE=1 and SCTLR.HA=0, meaning the hardware won't write-back to
the page tables to e.g. update the access flag.

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