Subject: Re: [PATCH 1/3] dt-bindings: iommu: arm-smmu-v3: Allow PMU child nodes

From: Peng Fan <[email-masked]>
Date: Thu, 9 Apr 2026 20:45:16 +0800

On Thu, Apr 09, 2026 at 10:10:38AM +0200, Krzysztof Kozlowski wrote:
>On Wed, Apr 08, 2026 at 03:51:15PM +0800, Peng Fan (OSS) wrote:
>> From: Peng Fan <[email-masked]>
>> 
>> The Arm SMMU v3 specification defines an optional PMCG (Performance
>
>"optional" in a meaning some SMMUv3 implementations do not have it?

Per SMMUv3 architecture:
Performance monitoring facilities are optional. When implemented, the SMMU has
one or more Performance Monitor Counter Groups (PMCG) associated with it.

>
>> Monitor Control Group) block. Per MMU-700 TRM, it has three 64KB pages,
>> with TCU Performance Monitor Counter Group (PMCG) registers starting at
>> offset 0x02000 in page 0. So PMCG could be described as a child node of the
>> SMMU in Devicetree.
>> 
>> Add a patternProperties entry to the arm,smmu-v3 binding to allow child
>> nodes matching "pmu@<addr>" and reference the existing
>> arm,smmu-v3-pmcg.yaml schema.
>> 
>> Signed-off-by: Peng Fan <[email-masked]>
>> ---
>>  Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> index 82957334bea24402b583e47eb61b5724c91e4378..1d09c5476e5f1a7c3e5c935b677641ee6cc9897e 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> @@ -50,6 +50,10 @@ properties:
>>              - cmdq-sync   # CMD_SYNC complete
>>              - priq        # PRI Queue not empty
>>  
>> +  '#address-cells': true
>
>Instead enum [1, 2]
>
>> +  '#size-cells': true
>
>Same here
>
>> +  ranges: true
>
>I guess only one mapping is allowed so:
>maxItems: 1

Accept above three comments.

>
>> +
>>    '#iommu-cells':
>>      const: 1
>>  
>> @@ -83,6 +87,12 @@ properties:
>>        register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
>>        doesn't support SMMU page1 register space.
>>  
>> +patternProperties:
>> +  '^pmu@[0-9a-f]+$':
>> +    type: object
>> +    $ref: /schemas/perf/arm,smmu-v3-pmcg.yaml#
>> +    unevaluatedProperties: false
>
>Please add another example with 4-space indentation.

ok.

Thanks,
Peng

>> +
>>  allOf:
>>    - if:
>>        not:
>> -- 
>> 2.37.1