Subject: Re: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits

From: Pranjal Shrivastava <[email-masked]>
Date: Thu, 7 May 2026 22:30:14 +0000

On Sun, May 03, 2026 at 06:54:12AM -0700, Nicolin Chen wrote:
> HTTU is introduced by utilizing the Dirty Bit Modifier (DBM) in the PTE.
> When kernel maps a clean but writable page, it will set PTE_READONLY and
> PTE_DBM (aka PTE_WRITE) at the same time. When a write occurs, an HTTU-
> capable MMU will automatically clear the PTE_RDONLY bit without software
> intervention.
> 
> On the other hand, SMMU has the same HTTU feature, yet it is not enabled
> in the SVA CD. As a result, SMMU will not clear the PTE_RDONLY bit while
> sharing the CPU page table, resulting in unnecessary stalls.
> 
> Thus, enable CTXDESC_CD_0_TCR_HA and CTXDESC_CD_0_TCR_HD in the SVA CD.
> 
> Suggested-by: Jason Gunthorpe <[email-masked]>
> Signed-off-by: Nicolin Chen <[email-masked]>
> ---
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
> index f1f8e01a7e914..1ed8a6f29dc44 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
> @@ -92,6 +92,16 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target,
>  
>  		target->data[1] = cpu_to_le64(virt_to_phys(mm->pgd) &
>  					      CTXDESC_CD_1_TTB0_MASK);
> +
> +		/*
> +		 * Enable Hardware Access and Dirty updates (DBM) if supported.
> +		 * This is safe to enable by default, as PTE_WRITE and PTE_DBM
> +		 * share the same bit.
> +		 */
> +		if (master->smmu->features & ARM_SMMU_FEAT_HA)
> +			target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA);
> +		if (master->smmu->features & ARM_SMMU_FEAT_HD)
> +			target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HD);

IIUC, we should be setting these if IO_PGTABLE_QUIRK_ARM_HD is present?

I think the driver maintains a clear distinction between HW capability 
(FEAT_HA/HD) and feature enablement (IO_PGTABLE_QUIRK_ARM_HD). 

We set IO_PGTABLE_QUIRK_ARM_HD during S1 domain finalize if 
IOMMU_HWPT_ALLOC_DIRTY_TRACKING flag is passed. Hence, we should check
for that flag OR IO_PGTABLE_QUIRK_ARM_HD before enabling these in CD..

Thanks,
Praan