From: Nicolin Chen <nicolinc@nvidia•com>
To: Jason Gunthorpe <jgg@nvidia•com>
Cc: Bjorn Helgaas <helgaas@kernel•org>, <will@kernel•org>,
<robin.murphy@arm•com>, <bhelgaas@google•com>, <joro@8bytes•org>,
<praan@google•com>, <baolu.lu@linux•intel.com>,
<kevin.tian@intel•com>, <miko.lenczewski@arm•com>,
<linux-arm-kernel@lists•infradead.org>, <iommu@lists•linux.dev>,
<linux-kernel@vger•kernel.org>, <linux-pci@vger•kernel.org>,
<dan.j.williams@intel•com>, <jonathan.cameron@huawei•com>,
<vsethi@nvidia•com>, <linux-cxl@vger•kernel.org>,
<nirmoyd@nvidia•com>
Subject: Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices
Date: Tue, 19 May 2026 18:04:18 -0700 [thread overview]
Message-ID: <ag0IkpcWvhQUfzf7@Asurada-Nvidia> (raw)
In-Reply-To: <20260520000504.GQ3602937@nvidia.com>
On Tue, May 19, 2026 at 09:05:04PM -0300, Jason Gunthorpe wrote:
> On Tue, May 19, 2026 at 06:48:01PM -0500, Bjorn Helgaas wrote:
> > On Tue, May 19, 2026 at 07:23:35PM -0300, Jason Gunthorpe wrote:
> > > On Tue, May 19, 2026 at 02:36:49PM -0500, Bjorn Helgaas wrote:
> > > > One motivation for putting this in the PCI core was to use the quirk
> > > > infrastructure, but this series doesn't use any of that. It doesn't
> > > > declare any fixups, e.g., DECLARE_PCI_FIXUP_FINAL, and it doesn't
> > > > update any state cached by the PCI core.
> > >
> > > It works like the acs quirks that are in the quirks file, which are
> > > also arguably only used by iommu too :)
> >
> > True, although ACS has a lot more PCI-specific grunge in it, including
> > all the "pci=config_acs" and "pci=disable_acs_redir" stuff.
> >
> > > I'm not keen on spreading lists of device ids for PCI quirks to iommu
> > > files, but it would be OK to move pci_ats_always_on() to
> > > iommu_ats_always_on() that calls the PCI quirk function.
> >
> > Yeah, I guess it's fair to collect the device IDs in PCI since this is
> > about characteristics of the device.
> >
> > If we leave stuff in drivers/pci/, I would prefer that part of it be
> > named to be purely informational, i.e., "CXL.cache_enabled" or
> > something similar that would also cover the NVIDIA devices.
>
> Yeah, that's fair, so let's rename it to
>
> pci_translated_required()
>
> ie the device requires translated requests to function. This is what
> CXL.cache implies (IIRC I was told the spec specifically says this)
>
> Requiring translated requests implies you have to enable ATS in the
> system.
Perhaps we could let IOMMU drivers check:
pci_cxl_is_cache_capable() || pci_dev_specific_is_pre_cxl()
directly?
Thanks
Nicolin
next prev parent reply other threads:[~2026-05-20 1:04 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-27 5:53 [PATCH v4 0/3] Allow ATS to be always on for certain ATS-capable devices Nicolin Chen
2026-04-27 5:54 ` [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices Nicolin Chen
2026-04-27 16:31 ` Dave Jiang
2026-04-30 21:41 ` Dan Williams (nvidia)
2026-04-30 23:28 ` Nicolin Chen
2026-05-01 23:27 ` Dan Williams (nvidia)
2026-05-01 23:46 ` Jason Gunthorpe
2026-05-02 0:19 ` Dan Williams (nvidia)
2026-05-19 19:36 ` Bjorn Helgaas
2026-05-19 22:23 ` Jason Gunthorpe
2026-05-19 23:48 ` Bjorn Helgaas
2026-05-20 0:05 ` Jason Gunthorpe
2026-05-20 1:04 ` Nicolin Chen [this message]
2026-05-20 14:20 ` Jason Gunthorpe
2026-05-20 17:29 ` Nicolin Chen
2026-05-20 17:47 ` Bjorn Helgaas
2026-05-20 17:56 ` Jason Gunthorpe
2026-05-20 13:12 ` Yi Liu
2026-05-20 14:34 ` Jason Gunthorpe
2026-05-21 7:31 ` Yi Liu
2026-05-21 13:05 ` Jason Gunthorpe
2026-05-22 9:18 ` Yi Liu
2026-05-25 6:58 ` Tian, Kevin
2026-04-27 5:54 ` [PATCH v4 2/3] PCI: Allow ATS to be always on for pre-CXL devices Nicolin Chen
2026-04-27 16:32 ` Dave Jiang
2026-05-20 13:12 ` Yi Liu
2026-05-20 17:50 ` Bjorn Helgaas
2026-05-20 17:53 ` Jason Gunthorpe
2026-04-27 5:54 ` [PATCH v4 3/3] iommu/arm-smmu-v3: Allow ATS to be always on Nicolin Chen
2026-04-27 16:37 ` Dave Jiang
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