Subject: Relax CPU features sanity checking on heterogeneous architectures

From: Sai Prakash Ranjan <[email-masked]>
Date: Fri, 11 Oct 2019 11:19:00 +0530

On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE arch, below 
warnings are observed during bootup of big cpu cores.

SM8150:

[    0.271177] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00000011112222, CPU4: 0x00000011111112
[    0.271184] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_ISAR4_EL1. Boot CPU: 0x00000000011142, CPU4: 0x00000000010142
[    0.271189] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_PFR1_EL1. Boot CPU: 0x00000010011011, CPU4: 0x00000010010000
[    0.271192] CPU features: Unsupported CPU feature variation detected.
[    0.271208] GICv3: CPU4: found redistributor 400 region 
0:0x0000000017ae0000
[    0.271237] CPU4: Booted secondary processor 0x0000000004 
[0x51df804e]
[    0.302919] Detected PIPT I-cache on CPU5
[    0.302930] CPU features: SANITY         CHECK: Unexpected variation 
in SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00000011112222, CPU5: 
0x00000011111112
[    0.302936] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_ISAR4_EL1. Boot CPU: 0x00000000011142, CPU5: 0x00000000010142
[    0.302941] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_PFR1_EL1. Boot CPU: 0x00000010011011, CPU5: 0x00000010010000
[    0.302957] GICv3: CPU5: found redistributor 500 region 
0:0x0000000017b00000
[    0.302987] CPU5: Booted secondary processor 0x0000000005 
[0x51df804e]
[    0.335066] Detected PIPT I-cache on CPU6
[    0.335076] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00000011112222, CPU6: 0x00000011111112
[    0.335082] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_ISAR4_EL1. Boot CPU: 0x00000000011142, CPU6: 0x00000000010142
[    0.335087] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_PFR1_EL1. Boot CPU: 0x00000010011011, CPU6: 0x00000010010000
[    0.335104] GICv3: CPU6: found redistributor 600 region 
0:0x0000000017b20000
[    0.335135] CPU6: Booted secondary processor 0x0000000006 
[0x51df804e]
[    0.367597] Detected PIPT I-cache on CPU7
[    0.367605] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00000011112222, CPU7: 0x00000011111112
[    0.367610] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_ISAR4_EL1. Boot CPU: 0x00000000011142, CPU7: 0x00000000010142
[    0.367615] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_PFR1_EL1. Boot CPU: 0x00000010011011, CPU7: 0x00000010010000
[    0.367632] GICv3: CPU7: found redistributor 700 region 
0:0x0000000017b40000
[    0.367661] CPU7: Booted secondary processor 0x0000000007 
[0x51df804e]

SC7180:

[    0.812770] CPU features: SANITY CHECK: Unexpected variation in 
SYS_CTR_EL0. Boot CPU: 0x00000084448004, CPU6: 0x0000009444c004
[    0.812838] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_AA64MMFR2_EL1. Boot CPU: 0x00000000001011, CPU6: 0x00000000000011
[    0.812876] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00000011112222, CPU6: 
0x1100000011111112
[    0.812924] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_ISAR4_EL1. Boot CPU: 0x00000000011142, CPU6: 0x00000000010142
[    0.812950] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_PFR0_EL1. Boot CPU: 0x00000010000131, CPU6: 0x00000010010131
[    0.812977] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_PFR1_EL1. Boot CPU: 0x00000010011011, CPU6: 0x00000010010000
[    0.813018] CPU features: Unsupported CPU feature variation detected.
[    0.813447] GICv3: CPU6: found redistributor 600 region 
0:0x0000000017b20000
[    0.814144] CPU6: Booted secondary processor 0x0000000600 
[0x51ff804f]
[    0.902441] Detected PIPT I-cache on CPU7
[    0.902528] CPU features: SANITY CHECK: Unexpected variation in 
SYS_CTR_EL0. Boot CPU: 0x00000084448004, CPU7: 0x0000009444c004
[    0.902591] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_AA64MMFR2_EL1. Boot CPU: 0x00000000001011, CPU7: 0x00000000000011
[    0.902610] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00000011112222, CPU7: 
0x1100000011111112
[    0.902659] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_ISAR4_EL1. Boot CPU: 0x00000000011142, CPU7: 0x00000000010142
[    0.902695] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_PFR0_EL1. Boot CPU: 0x00000010000131, CPU7: 0x00000010010131
[    0.902713] CPU features: SANITY CHECK: Unexpected variation in 
SYS_ID_PFR1_EL1. Boot CPU: 0x00000010011011, CPU7: 0x00000010010000
[    0.903217] GICv3: CPU7: found redistributor 700 region 
0:0x0000000017b40000
[    0.903965] CPU7: Booted secondary processor 0x0000000700 
[0x51ff804f]

Can we relax some sanity checking for these by making it FTR_NONSTRICT 
or by some other means? I just tried below roughly for SM8150 but I 
guess this is not correct,
maybe for ftr_generic_32bits we should be checking bootcpu and nonboot 
cpu partnum(to identify big.LITTLE) and then make it nonstrict?
These are all my wild assumptions, please correct me if I am wrong.

diff --git a/arch/arm64/kernel/cpufeature.c 
b/arch/arm64/kernel/cpufeature.c
index cabebf1a7976..207197692caa 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -164,8 +164,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] 
= {
         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 
ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
         /* Linux doesn't care about the EL3 */
         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 
ID_AA64PFR0_EL3_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
ID_AA64PFR0_EL2_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 
ID_AA64PFR0_EL2_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 
ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
         ARM64_FTR_END,
  };
@@ -345,10 +345,10 @@ static const struct arm64_ftr_bits 
ftr_generic_32bits[] = {
         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 
0),
         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 
0),
         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 
0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 
0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 12, 4, 
0),
         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 4, 4, 
0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 0, 4, 
0),
         ARM64_FTR_END,
  };

Thanks,
Sai

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